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LSM6DSTX Datasheet(PDF) 95 Page - STMicroelectronics |
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LSM6DSTX Datasheet(HTML) 95 Page - STMicroelectronics |
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95 / 175 page ![]() 11.10 SPI2_INT_OIS (6Fh) OIS interrupt configuration register and accelerometer self-test enable setting. The auxiliary SPI interface can write this register when the OIS_CTRL_FROM_UI bit in the FUNC_CFG_ACCESS (01h) register is equal to 0 (SPI2 full-control mode). This register is read-only when the OIS_CTRL_FROM_UI bit is equal to 1 (primary IF full-control mode) and shows the content of the UI_INT_OIS (6Fh) register. Table 216. SPI_INT_OIS register INT2_ DRDY_OIS LVL2_OIS DEN_LH_OIS - - 0(1) ST1_XL_ OIS ST0_XL_ OIS 1. This bit must be set to 0 for the correct operation of the device. Table 217. SPI_INT_OIS register description INT2_DRDY_OIS Enables OIS chain DRDY on the INT2 pin. This setting has priority over all other INT2 settings. LVL2_OIS Enables level-sensitive latched mode on the OIS chain. Default value: 0 DEN_LH_OIS Indicates polarity of DEN signal on OIS chain (0: DEN pin is active-low; 1: DEN pin is active-high) ST[1:0]_XL_OIS Selects accelerometer self-test - active only if the accelerometer OIS chain is enabled. Default value: 00 (00: normal mode; 01: positive sign self-test; 10: negative sign self-test; 11: reserved) LSM6DSTX SPI2_INT_OIS (6Fh) DS14039 - Rev 1 page 95/175 |
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