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UPSD3422 Datasheet(PDF) 123 Page - STMicroelectronics

Part # UPSD3422
Description  Turbo Plus series Fast Turbo 8032 MCU with USB and programmable logic
PDF  300 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

UPSD3422 Datasheet(HTML) 123 Page - STMicroelectronics

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Obsolete
Product(s)
- Obsolete
Product(s)
Obsolete
Product(s)
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Product(s)
UPSD3422, UPSD3433, UPSD3434, UPSD3454
I2C interface
123/300
23
I2C interface
UPSD34xx devices support one serial I2C interface. This is a two-wire communication
channel, having a bidirectional data signal (SDA, pin P3.6) and a clock signal (SCL, pin
P3.7) based on open-drain line drivers, requiring external pull-up resistors, RP, each with a
typical value of 4.7k
Ω (see Figure 40).
23.1
I2C interface main features
Byte-wide data is transferred, MSB first, between a Master device and a Slave device on two
wires. More than one bus Master is allowed, but only one Master may control the bus at any
given time. Data is not lost when another Master requests the use of a busy bus because
I2C supports collision detection and arbitration. The bus Master initiates all data movement
and generates the clock that permits the transfer. Once a transfer is initiated by the Master,
any device addressed is considered a Slave. Automatic clock synchronization allows I2C
devices with different bit rates to communicate on the same physical bus. A single device
can play the role of Master or Slave, or a single device can be a Slave only. Each Slave
device on the bus has a unique address, and a general broadcast address is also available.
A Master or Slave device has the ability to suspend data transfers if the device needs more
time to transmit or receive data.
This I2C interface has the following features:
●
Serial I/O Engine (SIOE): serial/parallel conversion; bus arbitration; clock generation
and synchronization; and handshaking are all performed in hardware
●
Interrupt or Polled operation
●
Multi-master capability
●
7-bit Addressing
●
Supports standard speed I2C (SCL up to 100kHz), fast mode I2C (101KHz to 400kHz),
and high-speed mode I2C (401KHz to 833kHz)
Figure 40.
Typical I2C bus configuration
1.
For 3.3 V system, connect RP to 3.3 V VCC. For 5.0 V system, connect RP to 5.0 V VDD.
I2C bus
SDA
SCL
RP
RP
VCC or VDD
(1)
Device with I2C
interface
Device with I2C
interface
SDA/P3.6
SCL/P3.7
uPSD34XX(V)
Device with I2C
Interface
AI09623c
Obsolete
Product(s)
- Obsolete
Product(s)



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