UPSD3422_V01 datasheet(126/300 Pages) STMICROELECTRONICS

126 / 300 page

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I2C interface

UPSD3422, UPSD3433, UPSD3434, UPSD3454

126/300

The interface may operate as either a Master or a Slave within a given application,

controlled by firmware writing to SFRs.

By default after a reset, the I2C interface is in Master Receiver mode, and the SDA/P3.6 and

SCL/P3.7 pins default to GPIO input mode, high impedance, so there is no I2C bus

interference. Before using the I2C interface, it must be initialized by firmware, and the pins

must be configured. This is discussed in Section 23.13: I2C operating sequences on

page 135.

23.4

Bus arbitration

A Master device always samples the I2C bus to ensure a bus line is high whenever that

Master is asserting a logic 1. If the line is low at that time, the Master recognizes another

device is overriding its own transmission.

A Master may start a transfer only if the I2C bus is not busy. However, it is possible that two

or more Masters may generate a Start condition simultaneously. In this case, arbitration

takes place on the SDA line each time SCL is high. The Master that first senses that its bus

sample does not correspond to what it is driving (SDA line is low while it is asserting a high)

will immediately change from Master-Transmitter to Slave-Receiver mode. The arbitration

process can carry on for many bit times if both Masters are addressing the same Slave

device, and will continue into the data bits if both Masters are trying to be Master-

Transmitter. It is also possible for arbitration to carry on into the acknowledge bits if both

Masters are trying to be Master-Receiver. Because address and data information on the bus

is determined by the winning Master, no information is lost during the arbitration process.

23.5

Clock synchronization

Clock synchronization is used to synchronize arbitrating Masters, or used as a handshake

by a devices to slow down the data transfer.

23.5.1

Clock sync during arbitration

During bus arbitration between competing Masters, Master_X, with the longest low period

on SCL, will force Master_Y to wait until Master_X finishes its low period before Master_Y

proceeds to assert its high period on SCL. At this point, both Masters begin asserting their

high period on SCL simultaneously, and the Master with the shortest high period will be the

first to drive SCL for the next low period. In this scheme, the Master with the longest low

SCL period paces low times, and the Master with the shortest high SCL period paces the

high times, making synchronized arbitration possible.

23.5.2

Clock sync during handshaking

This allows receivers in different devices to handle various transfer rates, either at the byte-

level, or bit-level.

At the byte-level, a device may pause the transfer between bytes by holding SCL low to have

time to store the latest received byte or fetch the next byte to transmit.

At the bit-level, a Slave device may extend the low period of SCL by holding it low. Thus the

speed of any Master device will adapt to the internal operation of the Slave.

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UPSD3422 Datasheet(PDF) 126 Page - STMicroelectronics

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