UPSD3422_V01 datasheet(129/300 Pages) STMICROELECTRONICS

129 / 300 page

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UPSD3422, UPSD3433, UPSD3434, UPSD3454

I2C interface

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23.8

I2C interface control register (S1CON)

Table 75.

Serial control register S1CON (SFR DCh, reset value 00h)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

CR2

ENI1

STA

STO

ADDR

CR[1:0]

Table 76.

S1CON register bit definition

Bit

Symbol

R/W

Function

7CR2

R,W

This bit, along with bits CR1 and CR0, determine the SCL

clock frequency (fSCL) when SIOE is in Master mode. These

bits create a clock divisor for fOSC. See Table 77.

6ENI1

R,W

I2C Interface Enable

0 = SIOE disabled, 1 = SIOE enabled. When disabled, both

SDA and SCL signals are in high impedance state.

5STA

R,W

START flag.

When set, Master mode is entered and SIOE generates a

Start condition only if the I2C bus is not busy. When a Start

condition is detected on the bus, the STA flag is cleared by

hardware. When the STA bit is set during an interrupt service,

the Start condition will be generated after the interrupt service.

4STO

R,W

STOP flag

When STO is set in Master mode, the SIOE generates a Stop

condition. When a Stop condition is detected, the STO flag is

cleared by hardware. When the STO bit is set during an

interrupt service, the Stop condition will be generated after the

interrupt service.

ADDR

R,W

This bit is set when an address byte received in Slave mode

matches the device address programmed into the S1ADR

2AA

R,W

Assert Acknowledge enable

If AA = 1, an acknowledge signal (low on SDA) is automatically

returned during the acknowledge bit-time on the SCL line

when any of the following three events occur:

SIOE in Slave mode receives an address that

matches contents of S1ADR register

A data byte has been received while SIOE is in

Master Receiver mode

A data byte has been received while SIOE is a

selected Slave Receiver

When AA = 0, no acknowledge is returned (high on SDA

during acknowledge bit-time).

1, 0

CR1, CR0

R,W

These bits, along with bit CR2, determine the SCL clock

frequency (fSCL) when SIOE is in Master mode. These bits

create a clock divisor for fOSC. See Table 77 for values.

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UPSD3422 Datasheet(PDF) 129 Page - STMicroelectronics

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