UPSD3422_V01 datasheet(132/300 Pages) STMICROELECTRONICS

132 / 300 page

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I2C interface

UPSD3422, UPSD3433, UPSD3434, UPSD3454

132/300

While transmitting, bytes are shifted out MSB first, and when receiving, bytes are shifted in

MSB first, through the Acknowledge Bit register as shown in Figure 42 on page 128.

23.10.1

Bus wait condition

After the SIOE finishes receiving a byte in Receive mode, or transmitting a byte in Transmit

mode, the INTR flag (in S1STA) is set and automatically a wait condition is imposed on the

I2C bus (SCL held low by SIOE). In Transmit mode, this wait condition is released as soon

as the MCU writes any byte to S1DAT. In Receive mode, the wait condition is released as

soon as the MCU reads the S1DAT register.

This method allows the user to handle transmit and receive operations within an interrupt

service routine. The SIOE will automatically stall the I2C bus at the appropriate time, giving

the MCU time to get the next byte ready to transmit or time to read the byte that was just

received.

23.11

I2C address register (S1ADR)

The S1ADR register (Table 82) holds the 7-bit device address used when the SIOE is

operating as a Slave. When the SIOE receives an address from a Master, it will compare

this address to the contents of S1ADR, as shown in Figure 42 on page 128.

If the 7 bits match, the INTR Interrupt flag (in S1STA) is set, and the ADDR Bit (in S1CON) is

set. The SIOE cannot modify the contents S1ADR, and S1ADR is not used during Master

mode.

Table 80.

S1DAT: I2C data shift register (SFR DEh, reset value 00h)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

S1DAT[7:0]

Table 81.

S1DAT register bit definition

Bit

Symbol

R/W

Function

7:0

S1DAT[7:0]

R/W

Holds the data byte to be transmitted in Transmit mode, or it

holds the data byte received in Receiver mode.

Table 82.

S1ADR: I2C address register (SFR DFh, reset value 00h)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

SLA6

SLA5

SLA4

SLA3

SLA2

SLA1

SLA0

–

Table 83.

S1ADR register bit definition

Bit

Symbol

R/W

Function

7:1

SLA[6:0]

R/W

Stores desired 7-bit device address, used when SIOE is in

Slave mode.

–

Not used

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