UPSD3422_V01 datasheet(143/300 Pages) STMICROELECTRONICS

143 / 300 page

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UPSD3422, UPSD3433, UPSD3434, UPSD3454

SPI (synchronous peripheral interface)

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24.1

SPI bus features and communication flow

The SPICLK signal is a gated clock generated from the UPSD34xx (Master) and regulates

the flow of data bits. The Master may transmit at a variety of baud rates, and the SPICLK

signal will clock one period for each bit of transmitted data. Data is shifted on one edge of

SPICLK and sampled on the opposite edge.

The SPITxD signal is generated by the Master and received by the Slave device. The

SPIRxD signal is generated by the Slave device and received by the Master. There may be

no more than one Slave device transmitting data on SPIRxD at any given time in a multi-

Slave configuration. Slave selection is accomplished when a Slave’s “Slave Select” (SS)

input is permanently grounded or asserted active-low by a Master device. Slave devices that

are not selected do not interfere with SPI activities. Slave devices ignore SPICLK and keep

their MISO output pins in high-impedance state when not selected.

The SPI specification allows a selection of clock polarity and clock phase with respect to

data. The UPSD34xx supports the choice of clock polarity, but it does not support the choice

of clock phase (phase is fixed at what is typically known as CPHA = 1). See Figure 45 and

Figure 46 on page 145 for SPI data and clock relationships.

Referring to these figures (45 and 46), when the phase mode is defined as such (fixed at

CPHA =1), in a new SPI data frame, the Master device begins driving the first data bit on

SPITxD at the very first edge of the first clock period of SPICLK.

The Slave device will use this first clock edge as a transmission start indicator, and therefore

the Slave’s Slave Select input signal may remain grounded in a single-Master/single-Slave

configuration (which means the user does not have to use the SPISEL signal from

UPSD34xx in this case).

The SPI specification does not specify high-level protocol for data exchange, only low-level

bit-serial transfers are defined.

24.2

Full-duplex operation

When an SPI transfer occurs, 8 bits of data are shifted out on one pin while a different 8 bits

of data are simultaneously shifted in on a second pin. Another way to view this transfer is

that an 8-bit shift register in the Master and another 8-bit shift register in the Slave are

connected as a circular 16-bit shift register. When a transfer occurs, this distributed shift

effectively exchanged (see Figure 44).

24.3

Bus-level activity

Figure 45 details an SPI receive operation (with respect to bus Master) and Figure 46

details an SPI transmit operation. Also shown are internal flags available to firmware to

manage data flow. These flags are accessed through a number of SFRs.

Note:

The UPSD34xx SPI interface SFRs allow the choice of transmitting the most significant bit

(MSB) of a byte first, or the least significant bit (LSB) first. The same bit-order applies to data

reception. Figures 45 and 46 illustrate shifting the LSB first.

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UPSD3422 Datasheet(PDF) 143 Page - STMicroelectronics

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