UPSD3422_V01 datasheet(146/300 Pages) STMICROELECTRONICS

146 / 300 page

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SPI (synchronous peripheral interface)

UPSD3422, UPSD3433, UPSD3434, UPSD3454

146/300

Figure 47.

SPI interface, master mode only

24.5

SPI configuration

The SPI interface is reset by the MCU reset, and firmware needs to initialize the SFRs

SPICON0, SPICON1, and SPICLKD to define several operation parameters.

The SPO Bit in SPICON0 determines the clock polarity. When SPO is set to '0,' a data bit is

transmitted on SPITxD from one rising edge of SPICLK to the next and is guaranteed to be

valid during the falling edge of SPICLK. When SPO is set to '1,' a data bit is transmitted on

SPITxD from one falling edge of SPICLK to the next and is guaranteed to be valid during the

rising edge of SPICLK. The UPSD34xx will sample received data on the appropriate edge of

SPICLK as determined by SPO. The effect of the SPO Bit can be seen in Figure 45 and

Figure 46 on page 145.

The FLSB Bit in SPICON0 determines the bit order while transmitting and receiving the 8-bit

data. When FLSB is '0,' the 8-bit data is transferred in order from MSB (first) to LSB (last).

When FLSB Bit is set to '1,' the data is transferred in order from LSB (first) to MSB (last).

The clock signal generated on SPICLK is derived from the internal PERIPH_CLK signal.

PERIPH_CLK always operates at the frequency, fOSC, and runs constantly except when

stopped in MCU Power Down mode. SPICLK is a result of dividing PERIPH_CLK by a sum

of different divisors selected by the value contained in the SPICLKD register. The default

value in SPICLKD after a reset divides PERIPH_CLK by a factor of 4. The bits in SPICLKD

can be set to provide resulting divisor values in of sums of multiples of 4, such as 4, 8, 12,

SPITDR - Transmit register

SPITxD / P1.6 or P4.6

Timing and control

(fOSC)

INTR

8032

SPIRDR - Receive register

8-bit SHIFT REGISTER

SPIRxD /

P1.5 or P4.5

SPICON0, SPICON1

- Control registers

SPISTAT - Status register

8032 MCU data bus

Clock

generate

SPISEL / P1.7 or P4.7

SPICLK / P1.4 or P4.4

Clock

divide

÷1

÷4

÷8

÷16

÷32

÷64

÷128

SPICLKD - Divide select

PERIPH_CLK

AI10486b

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UPSD3422 Datasheet(PDF) 146 Page - STMicroelectronics

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