UPSD3422_V01 datasheet(145/300 Pages) STMICROELECTRONICS

145 / 300 page

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UPSD3422, UPSD3433, UPSD3434, UPSD3454

SPI (synchronous peripheral interface)

145/300

Figure 46.

SPI transmit operation example

24.4

SPI SFR registers

Six SFR registers control the SPI interface:

●

SPICON0 (Table 89) for interface control

●

SPICON1 (Table 91) for interrupt control

●

SPITDR (SFR D4h, Write only) holds byte to transmit

●

SPIRDR (SFR D5h, Read only) holds byte received

●

SPICLKD (Table 93) for clock divider

●

SPISTAT (Table 95 on page 149) holds interface status

The SPI interface functional block diagram (Figure 47) shows these six SFRs. Both the

transmit and receive data paths are double-buffered, meaning that continuous transmitting

or receiving (back-to-back transfer) is possible by reading from SPIRDR or writing data to

SPITDR while shifting is taking place. There are a number of flags in the SPISTAT register

that indicate when it is full or empty to assist the 8032 MCU in data flow management. When

enabled, these status flags will cause an interrupt to the MCU.

Bit0

SPICLK

(SPO=0)

SPICLK

(SPO=1)

SPITXD

Bit1

Bit7

Bit0

Bit1

Bit7

1 frame

TISF

TEISF

BUSY

SPIINTR

SPITDR Empty

interrupt requested

Interrupt handler

write data in TDR

SPITDR Empty

interrupt requested

Transmit End

interrupt requested

SPISEL

AI07854

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