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UPSD3422 Datasheet(PDF) 148 Page - STMicroelectronics

Part # UPSD3422
Description  Turbo Plus series Fast Turbo 8032 MCU with USB and programmable logic
PDF  300 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

UPSD3422 Datasheet(HTML) 148 Page - STMicroelectronics

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Obsolete
Product(s)
- Obsolete
Product(s)
Obsolete
Product(s)
- Obsolete
Product(s)
SPI (synchronous peripheral interface)
UPSD3422, UPSD3433, UPSD3434, UPSD3454
148/300
3SSEL
RW
Slave Selection
0 = SPISEL output pin is constant logic '1' (slave device not
selected)
1 = SPISEL output pin is logic '0' (slave device is selected)
during data transfers
2FLSB
RW
First LSB
0 = Transfer the most significant bit (MSB) first
1 = Transfer the least significant bit (LSB) first
1
SPO
–
Sampling Polarity
0 = Sample transfer data at the falling edge of clock (SPICLK
is '0' when idle)
1 = Sample transfer data at the rising edge of clock (SPICLK is
'1' when idle)
0
–
–
Reserved
Table 91.
SPICON1: SPI interface control register 1 (SFR D7h, reset value 00h)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
––
––
TEIE
RORIE
TIE
RIE
Table 92.
SPICON1 register bit definition
Bit
Symbol
R/W
Definition
7-4
–
–
Reserved
3TEIE
RW
Transmission End Interrupt Enable
0 = Disable Interrupt for Transmission End
1 = Enable Interrupt for Transmission End
2RORIE
RW
Receive Overrun Interrupt Enable
0 = Disable Interrupt for Receive Overrun
1 = Enable Interrupt for Receive Overrun
1TIE
RW
Transmission Interrupt Enable
0 = Disable Interrupt for SPITDR empty
1 = Enable Interrupt for SPITDR empty
0RIE
RW
Reception Interrupt Enable
0 = Disable Interrupt for SPIRDR full
1 = Enable Interrupt for SPIRDR full
Table 93.
SPICLKD: SPI prescaler (clock divider) register (SFR D2h, reset value
04h)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
DIV128
DIV64
DIV32
DIV16
DIV8
DIV4
–
–
Table 90.
SPICON0 register bit definition (continued)
Bit
Symbol
R/W
Definition
Obsolete
Product(s)
- Obsolete
Product(s)



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