UPSD3422_V01 datasheet(151/300 Pages) STMICROELECTRONICS

151 / 300 page

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- Obsolete

Product(s)

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UPSD3422, UPSD3433, UPSD3434, UPSD3454

USB interface

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Figure 48.

USB module block diagram

25.1

Basic USB concepts

The Universal Serial Bus (USB) is more complex than the standard serial port and requires

familiarity with the specification to fully understand how to use the USB peripheral in the

UPSD34xx. The USB specification is available on the Internet at http://www.usb.org.

Some basic concepts will be presented in this section but knowledge of the USB

specification is required.

In a USB system, there is only one master and the master is the host computer. The host

controls all activity on the bus and devices respond to requests from the host. The only

exception is when a device has been put into a low power suspend mode by the host. In this

case, the device can signal a remote wakeup. Outside of that exception, all activity is

controlled and initiated by the host. The host-centric model versus a peer-to-peer model

provides the best way to develop low cost peripherals by keeping the complex control logic

on the host side. The UPSD34xx is a peripheral (non-host) device.

25.1.1

Communication flow

The USB provides a means for communication between host (client) software and a function

on a USB device. Functions can have different requirements for the communication flow

depending on the client software to the USB function interaction. With USB, the various

communication flows are separated to provide better bus utilization. For example, one

communication flow is used for managing the device while another is for transferring data

related to the operation of the device. Some bus access is used for each communication

flow with each flow terminated at an endpoint on a device. Each endpoint has various

aspects associated with the communication flow. A USB device looks like a collection of

endpoints to the USB system.

8032

MCU

USB SFRs

USB

transceiver

Serial

interface

rngine

PLL

Clock

CTRL and data

CTRL

XDATA

D–

D+

USB–

USB+

AI10488

Endpoint4

3 - 40 MHz

48 MHz

Endpoint0

Endpoint4

Endpoint0

IN FIFOs (64 bytes each)

OUT FIFOs (64 bytes each)

SETUP command

buffer (8 bytes)

FIFO interface logic

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Product(s)

- Obsolete

Product(s)

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