UPSD3422_V01 datasheet(150/300 Pages) STMICROELECTRONICS

150 / 300 page

Obsolete

Product(s)

- Obsolete

Product(s)

Obsolete

Product(s)

- Obsolete

Product(s)

USB interface

UPSD3422, UPSD3433, UPSD3434, UPSD3454

150/300

USB interface

UPSD34xx devices provide a full speed USB (Universal Serial Bus) device interface. The

serial interface engine (SIE) provides the interface between the CPU and the USB (see

Figure 48).

Note:

For a list of known limitations of USB interface for UPSD34xx devices, please refer to

Section 34: Important notes on page 294.

Please make sure you have the latest 3400 USB firmware.

The USB module supports the following features:

●

USB 2.0 compliant to full-speed mode (12 Mbps)

●

3.3 V USB transceiver

●

Five endpoints including Control endpoint 0

–

Each endpoint includes two 64 byte FIFOs, one for IN and one for OUT

transactions

–

Endpoints 1 through 4 support Interrupt and Bulk transfers

●

USB Bus Suspend detection and Resume generation

●

PLL Multiplier to generate the 48 MHz as required for USB support.

●

Interrupts for various USB bus conditions.

●

Performs NRZI encoding and decoding, bit stuffing, CRC generation and checking, and

serial/parallel data conversion

●

Double buffering (using FIFO pairing) for efficient data transfer in Bulk transfer

●

Busy bit-based FIFO status monitoring

●

FIFOs accessible via XDATA space

The analog front-end of the USB module is an on-chip USB transceiver. It is designed to

allow voltage levels equal to VDD from the standard logic to interface with the physical layer

of the USB. It is capable of receiving and transmitting serial data at full speed (12 Mb/s).

The SIE is the digital-front-end of the USB block. This module recovers the 12MHz clock,

detects the USB sync word, and handles all low-level USB protocols and error checking.

The bit-clock recovery circuit recovers the clock from the incoming USB data stream and is

able to track jitter and frequency drift according to the USB specifications.

The SIE also translates the electrical USB signals into bytes or signals. When there is a

USB device address match, the USB data is directed to an endpoint’s FIFO for OUT

transactions and read from an endpoint’s FIFO for IN transactions. Control transfers are

supported on Endpoint0 and interrupt and bulk data transfers are supported on Endpoints1

through 4. The device’s USB address and the enabling of the endpoints are programmable

using the SIE’s SFRs.

Important note: The USB SIE requires a 48MHz clock to operate properly. A PLL is included

in the UPSD34xx that must be programmed appropriately based on the input clock to

provide a 48MHz clock to the SIE (see Section 14.2.2: USB_CLK on page 69 to set up the

PLL).

Obsolete

Product(s)

- Obsolete

Product(s)

UPSD3422 Datasheet(PDF) 150 Page - STMicroelectronics

UPSD3422 Datasheet(HTML) 150 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL