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UPSD3422 Datasheet(PDF) 149 Page - STMicroelectronics |
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UPSD3422 Datasheet(HTML) 149 Page - STMicroelectronics |
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149 / 300 page  Obsolete Product(s) - Obsolete Product(s) Obsolete Product(s) - Obsolete Product(s) UPSD3422, UPSD3433, UPSD3434, UPSD3454 SPI (synchronous peripheral interface) 149/300 Table 94. SPICLKD register bit definition Bit Symbol R/W Definition 7DIV128 RW 0 = No division 1 = Divide fOSC clock by 128 6DIV64 RW 0 = No division 1 = Divide fOSC clock by 64 5DIV32 RW 0 = No division 1 = Divide fOSC clock by 32 4DIV16 RW 0 = No division 1 = Divide fOSC clock by 16 3DIV8 RW 0 = No division 1 = Divide fOSC clock by 8 2DIV4 RW 0 = No division 1 = Divide fOSC clock by 4 1-0 Not Used – Table 95. SPISTAT: SPI interface status register (SFR D3h, reset value 02h) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 – – – BUSY TEISF RORISF TISF RISF Table 96. SPISTAT register bit definition Bit Symbol R/W Definition 7-5 – – Reserved 4BUSY R SPI Busy 0 = Transmit or Receive is completed 1 = Transmit or Receive is in process 3 TEISF R Transmission End Interrupt Source flag 0 = Automatically resets to '0' when firmware reads this register 1 = Automatically sets to '1' when transmission end occurs 2 RORISF R Receive Overrun Interrupt Source flag 0 = Automatically resets to '0' when firmware reads this register 1 = Automatically sets to '1' when receive overrun occurs 1TISF R Transfer Interrupt Source flag 0 = Automatically resets to '0' when SPITDR is full (just after the SPITDR is written) 1 = Automatically sets to '1' when SPITDR is empty (just after byte loads from SPITDR into SPI shift register) 0RISF R Receive Interrupt Source flag 0 = Automatically resets to '0' when SPIRDR is empty (after the SPIRDR is read) 1 = Automatically sets to '1' when SPIRDR is full Obsolete Product(s) - Obsolete Product(s) |
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