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UPSD3422 Datasheet(PDF) 198 Page - STMicroelectronics |
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UPSD3422 Datasheet(HTML) 198 Page - STMicroelectronics |
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198 / 300 page  Obsolete Product(s) - Obsolete Product(s) Obsolete Product(s) - Obsolete Product(s) PSD module UPSD3422, UPSD3433, UPSD3434, UPSD3454 198/300 28.2.1 8032 program address space In the example of Figure 63, six sectors of Main Flash memory (fs2.. fs7) are paged across three memory pages in the upper half of program address space, and the remaining two sectors of Main Flash memory (fs0, fs1) reside in the lower half of program address space, and these two sectors are independent of paging (they reside in “common” program address space). This paged memory example is quite common and supported by many 8051 software compilers. 28.2.2 8032 data address space (XDATA) Four sectors of Secondary Flash memory reside in the upper half of 8032 XDATA space in the example of Figure 63. SRAM and csiop registers are in the lower half of XDATA space. The 8032 SFR registers and local SRAM inside the 8032 MCU module do not reside in XDATA space, so it is OK to place PSD module SRAM or csiop registers at an address that overlaps the address of internal 8032 MCU module SRAM and registers. Figure 63. Typical system memory map 28.2.3 Specifying the memory map with PSDsoft express The memory map example shown in Figure 63 on page 198 is implemented using PSDsoft Express in a point-and-click environment. PSDsoft Express will automatically generate Hardware Definition Language (HDL) statements of the ABEL language for the DPLD, such as those shown in Table 159. Specifying these equations using PSDsoft Express is very simple. For example, Figure 64, page 84 shows how to specify the chip-select equation for the 16 Kbyte Flash memory segment, fs4. Notice fs4 is on memory page 1. This specification process is repeated for all other Flash memory segments, the SRAM, the csiop register block, and any external chip select signals that may be needed. 0000h 8000h A000h C000h E000h FFFFh 8032 XDATA SPACE (RD and WR) 8032 PROGRAM SPACE (PSEN) csboot0 8KB csboot1 8KB csboot2 8KB csboot3 8KB Page X fs0, 16KB Common Memory to All Pages fs7 16KB fs5 16KB fs3 16KB rs0, 8KB Page 0 Page 2 Page 1 2000h 0000h 8000h FFFFh System I/O fs6 16KB fs4 16KB fs2 16KB fs1, 16KB Common Memory to All Pages C000h 4000h csiop 256B AI09173 Obsolete Product(s) - Obsolete Product(s) |
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