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UPSD3422 Datasheet(PDF) 200 Page - STMicroelectronics |
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UPSD3422 Datasheet(HTML) 200 Page - STMicroelectronics |
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200 / 300 page  Obsolete Product(s) - Obsolete Product(s) Obsolete Product(s) - Obsolete Product(s) PSD module UPSD3422, UPSD3433, UPSD3434, UPSD3454 200/300 maintained by alternating between the two flash sectors. For example, a data set of 128 bytes is written and maintained by software in a distributed fashion across one 8 Kbyte sector of Secondary Flash memory until it becomes full. Then the writing continues on the other 8 Kbyte sector while erasing the first 8 Kbyte sector. This process repeats continuously, bouncing back and forth between the two 8 Kbyte sectors. This creates a wear-leveling effect, which increases the effective number of erase cycles for a data set of 128 bytes to many times more than the base 100 000 erase cycles of the Flash memory. EEPROM emulation in Flash memory is typically faster than writing to actual EEPROM memory, and more reliable because the last known value in a data set is maintained even if a WRITE cycle is corrupted by a power outage. The EEPROM emulation function can be called by the user’s firmware, making it appear that the user is writing a single byte, or data record, thus hiding all of the data management that occurs within the two 8 Kbyte Flash sectors. EEPROM emulation firmware for the UPSD34xx is available from www.st.com/psm. 28.2.5 Alternative mapping schemes Here are more possible memory maps for the UPSD3433. Note: Mapping examples would be slightly different for UPSD3433 and UPSD3434, because of the different sizes of individual Flash memory sectors. ● Figure 65 Place the larger Main Flash Memory into program space, but split the Secondary Flash in half, placing two of its sectors into XDATA space and remaining two sectors into program space. This method allows the designer to put IAP code (or boot code) into two sectors of Secondary Flash in program space, and use the other two Secondary Flash sectors for data storage, such as EEPROM emulation in XDATA space. ● Figure 66 Place both the Main and Secondary Flash memories into program space for maximum code storage, with no Flash memory in XDATA space. Figure 65. Mapping: split second Flash in half 0000h 8000h 4000h 6000h FFFFh 8032 XDATA SPACE (RD and WR) 8032 PROGRAM SPACE (PSEN) csboot1, 8KB Common Memory to All Pages csboot0, 8KB Common Memory to All Pages csboot2 8KB csboot3 8KB Page X rs0, 8KB csiop, 256B fs7 16KB fs3 16KB fs1 16KB Page 0 Page 1 Page 2 Page 3 2000h 0000h 8000h FFFFh Nothing Mapped fs6 16KB fs5 16KB fs4 16KB fs2 16KB fs0 16KB System I/O System I/O C000h 2100h 4000h 2000h AI09174 Obsolete Product(s) - Obsolete Product(s) |
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