UPSD3422_V01 datasheet(196/300 Pages) STMICROELECTRONICS

196 / 300 page

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PSD module

UPSD3422, UPSD3433, UPSD3434, UPSD3454

196/300

Note:

Four pins on Port C are dedicated to JTAG, leaving four pins for general I/O.

Each I/O pin on the PSD module can be individually configured for different functions on a

pin-by-pin basis (Figure 79 on page 232). Following are the available functions on PSD

module I/O pins.

●

MCU I/O: 8032 controls the output state of each port pin or it reads input state of each

port pin, by accessing csiop registers at run-time. The direction (in or out) of each pin is

also controlled by csiop registers at run-time.

●

PLD I/O: PSDsoft Express logic equations and pin configuration selections determine if

pins are connected to OMC outputs or IMC inputs. This is a static and non-volatile

configuration. Port pins connected to PLD outputs can no longer be driven by the 8032

using MCU I/O output mode.

●

Latched MCU Address Output: Port A or Port B can output de-multiplexed 8032

address signals A0 - A7 on a pin-by-pin basis as specified in csiop registers at run-

time. In addition, Port B can also be configured to output de-multiplexed A8-A15 in

PSDsoft Express.

●

Data Bus Repeater: Port A can bidirectionally buffer the 8032 data bus (de-

multiplexed) for a specified address range in PSDsoft Express. This is referred to as

Peripheral I/O Mode in this document.

●

Open Drain Outputs: Some port pins can function as open-drain as specified in csiop

registers at run-time.

●

Pins on Port D can be used for external chip-select outputs originating from the

DPLD, without consuming OMC resources within the GPLD.

28.1.15

JTAG port

In-System Programming (ISP) can be performed through the JTAG signals on Port C. This

serial interface allows programming of the entire PSD module device or subsections of the

PSD module (for example, only Flash memory but not the PLDs) without the participation of

the 8032. A blank UPSD34xx device soldered to a circuit board can be completely

programmed in 10 to 25 seconds. The four basic JTAG signals on Port C; TMS, TCK, TDI,

and TDO form the IEEE-1149.1 interface. The PSD module does not implement the IEEE-

1149.1 Boundary Scan functions, but uses the JTAG interface for ISP an 8032 debug. The

PSD module can reside in a standard JTAG chain with other JTAG devices and it will remain

in BYPASS mode when other devices perform JTAG functions.

ISP programming time can be reduced as much as 30% by using two optional JTAG signals

on Port C, TSTAT and TERR, in addition to TMS, TCK, TDI and TDO, and this is referred to

as “6-pin JTAG”. The FlashLINK JTAG programming cable is available from

STMicroelectronics and PSDsoft Express software is available at no charge from

www.st.com/psm. More JTAG ISP information maybe found in Section 28.6.1: JTAG ISP and

JTAG debug on page 257.

The MCU module is also included in the JTAG chain within the UPSD34xx device for 8032

debugging and emulation. While debugging, the PSD module is in BYPASS mode.

Conversely, during ISP, the MCU module is in BYPASS mode.

Table 158.

General I/O pins on PSD module

Pkg

Port A

Port B

Port C

Port D

Total

52-pin

0841

80-pin

8842

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UPSD3422 Datasheet(PDF) 196 Page - STMicroelectronics

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