UPSD3422_V01 datasheet(192/300 Pages) STMICROELECTRONICS

192 / 300 page

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PSD module

UPSD3422, UPSD3433, UPSD3434, UPSD3454

192/300

28.1

PSD module functional description

Major functional blocks are shown in Figure 61 on page 191. The next sections describe

each major block.

28.1.1

8032 address/data/control interface

These signals attach directly to the MCU module to implement a 16-bit multiplexed 8051-

style bus between the two stacked die. The MCU instruction prefetch and branch cache

logic resides on the MCU module, leaving a modified 8051-style memory interface on the

PSD module.

The active-low reset signal originating from the MCU module goes to the PSD module reset

input (RST). This reset signal can then be routed as an external output from the UPSD34xx

to the system PC board, if needed, through any one of the PLD output pins as active-high or

active-low logic by specifying logic equations in PSDsoft Express.

The 8032 address and data busses are routed throughout the PSD module as shown in

Figure 61 connecting many elements on the PSD module to the 8032 MCU. The 8032 bus is

not only connected to the memories, but also to the General PLD, making it possible for the

8032 to directly read and write individual logic macrocells inside the General PLD.

28.1.2

Dual Flash memories and IAP

UPSD34xx devices contain two independent Flash memory arrays. This means that the

8032 can read instructions from one Flash memory array while erasing or writing the other

Flash memory array. Concurrent operation like this enables robust remote updates of

firmware, also known as In-Application Programming (IAP). IAP can occur using any

UPSD34xx interface (e.g., UART, I2C, SPI). Concurrent memory operation also enables the

designer to emulate EEPROM memory within either of the two Flash memory arrays for

small data sets that have frequent updates.

The 8032 can erase Flash memories by individual sectors or it can erase an entire Flash

memory array at one time. Each sector in either Flash memory may be individually write

protected, blocking any WRITEs from the 8032 (good for boot and start-up code protection).

The Flash memories automatically go to standby between 8032 READ or WRITE accesses

to conserve power. Minimum erase cycles is 100K and minimum data retention is 15 years.

Flash memory, as well as the entire PSD module may be programmed with the JTAG In-

System Programming (ISP) interface with no 8032 involvement, good for manufacturing and

lab development.

28.1.3

Main Flash memory

The Main Flash memory is divided into equal sized sectors that are individually selectable

by the Decode PLD output signals, named FSx, one signal for each Main Flash memory

sector. Each Flash sector can be located at any address within 8032 program address

space (accessed with PSEN) or data address space, also known as 8032 XDATA space

(accessed with RD or WR), as defined with the software development tool, PSDsoft

Express. The user only has to specify an address range for each segment and specify if

Main Flash memory will reside in 8032 data or program address space, and then PSEN, RD,

or WR are automatically activated for the specified range. 8032 firmware is easily

programmed into Main Flash memory using PSDsoft Express or other software tools. See

Table 157 on page 193 for Main Flash sector sizes on the various UPSD34xx devices.

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UPSD3422 Datasheet(PDF) 192 Page - STMicroelectronics

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