UPSD3422_V01 datasheet(188/300 Pages) STMICROELECTRONICS

188 / 300 page

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Programmable counter array (PCA) with PWM

UPSD3422, UPSD3433, UPSD3434, UPSD3454

188/300

3–

Reserved

210B_PWM

0 = Select 16-bit PWM

1 = Select 10-bit PWM

1-0

CLK_SEL

[1:0]

00 Select Prescaler clock as Counter clock

01 Select Timer 0 Overflow

10 Select External Clock pin (P4.3 for PCA0) (MAX clock rate = fOSC/4)

Table 150.

PCA1 control register PCACON1 (SFR 0BCh, reset value 00h)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

–

EN_PCA

EOVFI

PCAIDLE

–

CLK_SEL[1:0]

Table 151.

PCA1 register bit definition

Bit

Symbol

Function

6EN_PCA

0 = PCA counter is disabled

1 = PCA counter is enabled

EN_PCA Counter Run Control Bit. Set with software to turn the PCA

counter on. Must be cleared with software to turn the PCA counter off.

EOVFI

1 = Enable Counter Overflow Interrupt if overflow flag (OVF) is set

4PCAIDLE

0 = PCA operates when CPU is in Idle Mode

1 = PCA stops running when CPU is in Idle Mode

3–

Reserved

210B_PWM

0 = Select 16-bit PWM

1 = Select 10-bit PWM

1-0

CLK_SEL

[1:0]

00 Select Prescaler clock as Counter clock

01 Select Timer 0 Overflow

10 Select External Clock pin (P4.7 for PCA1) (MAX clock rate = fOSC/4)

Table 152.

PCA status register PCASTA (SFR 0A5h, reset value 00h)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

OVF1

INTF5

INTF4

INTF3

OVF0

INTF2

INTF1

INTF0

Table 153.

PCASTA register bit definition

Bit

Symbol

Function

7OFV1

PCA1 Counter OverFlow flag

Set by hardware when the counter rolls over. OVF1 flags an interrupt if Bit

EOVFI in PCACON1 is set. OVF1 may be set with either hardware or

software but can only be cleared with software.

6INTF5

TCM5 Interrupt flag

Set by hardware when a match or capture event occurs.

Must be clear with software.

Table 149.

PCA0 register bit definition (continued)

Bit

Symbol

Function

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UPSD3422 Datasheet(PDF) 188 Page - STMicroelectronics

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