EFP01 datasheet(51/158 Pages) SILABS

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Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

DC line regulation

LINEREG

Buck mode3

—

1.40

—

mV/V

VOC in parallel with VOA, LDO

mode, 3

—

2.6

—

mV/V

DC load regulation

LOADREG

Buck mode3

—

0.07

—

mV/mA

VOC in parallel with VOA, LDO

mode, 3

—

0.13

—

mV/mA

Output voltage range,

Coarse Regulator enabled

VVOA_COARSE

EM4, 0 µA < ILOAD < 100 µA

1.69

—

MIN(3.40,

VDDB)

Output load current, Coarse

Regulator enabled

ILOAD_COARSE

EM4, VOA output within

V_VOA_COARSE range

—

100

µA

Nominal inductor, 20% toler-

ance

LDCDCA

Wired buck configuration, VDDB -

VOA > 3.0V

—

3.3

—

µH

Wired buck configuration, VDDB -

VOA ≤ 3.0V

—

2.2

—

µH

Startup time from output en-

abled to output within 1% of

final target voltage4

TSTART

Wired buck with LDO (VOA),

BB_IPK = 18, ILOAD = 10 mA

—

247

—

µs

Note:

1. Maximum output load current is determined by first measuring the output voltage with a 5mA load. Maximum output load is the

maximum load at which measured output voltage is no lower than 50mV from the original 5mA load measured voltage.

2. With less than 660 mV of headroom in buck mode, TON will be limited and the desired peak current can never be reached, result-

ing in a reduction in output load current. BB_TON_MAX = 7 (2030ns) supports the lowest headroom.

3. Specifications assume minimum headroom requirement has been met if (i.e., VDDB - VOA > 660mV, if operating in buck DCDC

mode, or VDDB - VOA > 365mV, if operating in LDO mode).

4. For converters enabled by default, total startup time will be TSTART + TBOOT (found in the General Operating Conditions table)

EFP01 Energy Friendly PMIC Family Data Sheet

Electrical Specifications

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