EFP01 datasheet(73/158 Pages) SILABS

73 / 158 page

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Output voltage range, coarse

regulator enabled6

VVOB_COARSE

EM4, 0 µA < ILOAD < 100 µA

1.69

—

MIN(3.40,

VDDB)

Output load current, coarse

regulator enabled6

ILOAD_COARSE

EM4, VOB output within

V_VOB_COARSE range

—

100

µA

Nominal inductor (20% Tol-

erance)

LDCDCB

VDDB - VOB > 3.0V

—

3.3

—

µH

VDDB - VOB ≤ 3.0V

—

2.2

—

µH

Startup time from output en-

abled to output within 1% of

final target voltage7,8

TSTART

Wired buck / wired buck with LDO

(VOB), BK_IPK = 18, ILOAD = 10

—

193

—

µs

Note:

1. In Single-Cell Boost (EFP0108) and Boost Bootstrap (EFP0111) configurations, the DCDC B input (VDDB) is powered by the

DCDC A output (VOA). Therefore, the maximum output current of DCDC B will also be limited by the maximum output current of

the DCDC A converter.

2. In Single-Cell Boost (EFP0108) and Boost Bootstrap (EFP0111) configurations, the DCDC B input (VDDB) is powered by the

DCDC A output (VOA). Therefore, the maximum output voltage of the VOB converter will be limited by the VOA output voltage.

3. Maximum output load current is determined by first measuring the output voltage with a 5mA load. Maximum output load is the

the maximum load at which measured output voltage is no lower than 50mV from the original 5mA load measured voltage.

4. With less than 660 mV of headroom in buck mode, TON will be limited and the desired peak current can never be reached, result-

ing in a reduction in output load current. BK_TON_MAX = 7 (2030ns) supports the lowest headroom.

5. Specifications assume minimum headroom requirement has been met if (i.e., VDDB - VOB > 660mV, if operating in buck DCDC

mode, or VDDB - VOB > 365mV, if operating in LDO mode).

6. For certain OPN variants, VOB is expected to drive an output in the range of 1.1V to 1.2V, and the maximum output voltage of the

converter is internally limited to 1.26V. Any programmed VOB_EM0_V or VOB_EM2_V values that would result in a voltage high-

er than 1.26V will not affect the output voltage. In addition, for these OPNs, the VOB coarse regulator and bypass functionality is

disabled in hardware (i.e., setting the enable bit has no effect).

7. For converters enabled by default, total startup time will be TSTART + TBOOT (found in the General Operating Conditions table)

8. For the EFP0109/11 OPNs where the VOB converter is enabled by default, the VOB converter won't be enabled until the VOA

converter has reached regulation.

EFP01 Energy Friendly PMIC Family Data Sheet

Electrical Specifications

silabs.com | Building a more connected world.

Rev. 1.3 | 73

EFP01 Datasheet(PDF) 73 Page - Silicon Laboratories

EFP01 Datasheet(HTML) 73 Page - Silicon Laboratories

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL