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ICS9LPRS477D Datasheet(PDF) 11 Page - Renesas Technology Corp |
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ICS9LPRS477D Datasheet(HTML) 11 Page - Renesas Technology Corp |
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11 / 27 page  9LPRS477D PROGRAMMABLE SYSTEM CLOCK CHIP FOR ATI RD790-K8TM BASED SYSTEMS IDT® PROGRAMMABLE SYSTEM CLOCK CHIP FOR ATI RD790-K8TM BASED SYSTEMS 11 9LPRS477D REV C 010715 SMBus Table: SB_SRC Frequency Select Register Byte 6 Name Control Function Type 0 1 Default Bit 7 ATIG SSEN ATIG Spread Enable RW Disable Enable 0 Bit 6 SB_SRC/CPU SSEN SB_SRC/CPU Spread Enable RW Disable Enable 0 Bit 5 SRC SSEN SRC Spread Enable RW Disable Enable 0 Bit 4 SB _SRC_FS4 SB_SRC Frequen cy Select MSB RW 0 Bit 3 SB _SRC_FS3 SB_S RC Frequency Select RW 1 Bit 2 SB _SRC_FS2 SB_SRC Frequency Select RW 1 Bit 1 SB _SRC_FS1 SB_S RC Frequency Select RW 1 Bit 0 SB _SRC_FS0 S B_SRC Frequency Select LSB RW 1 SMBus Table: Device ID register Byte 7 Name Control Function Type 0 1 Default Bit 7 Device ID7 R x Bit 6 Device ID6 R x Bit 5 Device ID5 R x Bit 4 Device ID4 R x Bit 3 Device ID3 R x Bit 2 Device ID2 R x Bit 1 Device ID1 R x Bit 0 Device ID0 R x SMBus Table: Vendor & Revision ID Register Byte 8 Name Control Function Type 0 1 Default Bit 7 RID3 R - - 0 Bit 6 RID2 R -- 1 Bit 5 RID1 R - - 0 Bit 4 RID0 R - - 0 Bit 3 VID3 R -- 0 Bit 2 VID2 R - - 0 Bit 1 VID1 R - - 0 Bit 0 VID0 R - - 1 SMBus Table: WatchDog Timer Control Register Byte 9 Name Control Function Type 0 1 Default Bit 7 HWD_EN Watchdog Hard Alarm Enable RW Disable and Reload Hartd Alarm Timer, Clear WD Hard status bit. Enable Timer 0 Bit 6 SWD_EN Watch dog Soft Alarm Enable RW Disable Enable 0 Bit 5 WD Hard Statu s WD Hard Alarm Status R Normal Alarm X Bit 4 WD Soft Status WD Soft Alarm S tatus R Normal Alarm X Bit 3 WDTCtrl Watch Dog Alarm Time base Control RW 290ms Base 1160ms Base 0 Bit 2 HWD2 WD Hard Alarm Timer Bit 2 RW 1 Bit 1 HWD1 WD Hard Alarm Timer Bit 1 RW 1 Bit 0 HWD0 WD Hard Alarm Timer Bit 0 RW 1 SMBus Table: WD Timer Safe Frequency Control Register Byte 10 Name Control Function Type 0 1 Default Bit 7 SWD2 WD Soft Alarm Timer Bit 2 RW 1 Bit 6 SWD1 WD Soft Alarm Timer Bit 1 RW 1 Bit 5 SWD0 WD Soft Alarm Timer Bit 0 RW 1 Bit 4 WD SF4 RW 0 Bit 3 WD SF3 RW 1 Bit 2 WD SF2 RW 1 Bit 1 WD SF1 RW 1 Bit 0 WD SF0 RW 1 SMBus Table: Byte Count Register Byte 11 Name Control Function Type 0 1 Default Bit 7 0 Bit 6 0 Bit 5 BC5 Byte Count bit 5 (MSB) RW 0 Bit 4 BC4 Byte Count bit 4 RW 0 Bit 3 BC3 Byte Count bit 3 RW 1 Bit 2 BC2 Byte Count bit 2 RW 1 Bit 1 BC1 Byte Count bit 1 RW 1 Bit 0 BC0 Byte Count bit 0 (LSB) RW 1 See S B_SRC Frequency Select Table Note: SB_SRC and CPU Clo cks are synchronous. Changing this frequency will alter the SB_SRC and CPU frequency by the same percentage. Devi ce ID 75 hex for 9LPRS477 REVISION ID VENDOR ID These bits represent the number of Watch Dog Time Base Units that pass before the Wa tch Alarm expires. Default is 7 X 290ms = 2s. These bits represent the number of Watch Dog Time Base Units that pass before the Wa tch Alarm expires. Default is 7 X 290ms = 2s. Watch Dog Safe Freq Programming bits These bits configure the safe frequency that the device returns to if the Watchdog Timer expires. The value show here corresponds to the power up default of the device. See the various Frequency Select Tables for the exact frequ encies. Reserved Reserved Determines the number of bytes that are read back from the device. Default is 0F hex. |
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