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ICS9LPRS477D Datasheet(PDF) 12 Page - Renesas Technology Corp |
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ICS9LPRS477D Datasheet(HTML) 12 Page - Renesas Technology Corp |
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12 / 27 page  9LPRS477D PROGRAMMABLE SYSTEM CLOCK CHIP FOR ATI RD790-K8TM BASED SYSTEMS IDT® PROGRAMMABLE SYSTEM CLOCK CHIP FOR ATI RD790-K8TM BASED SYSTEMS 12 9LPRS477D REV C 010715 SMBus Table: M/N Programming Enable and I/O Vout Control Register Byte 12 Name Control Function Type 0 1 Default Bit 7 CPU M/N En CPU PLL M/N Prog. Enable RW M/N Prog. Disabled M/N Prog. Enabled 0 Bit 6 SRC M/N En SRC M/N Prog.Enable RW M/N Prog. Disabled M/N Prog. Enabled 0 Bit 5 ATIG M/N En ATIG M/N Prog. Enable RW M/N Prog. Disabled M/N Prog. Enabled 0 Bit 4 SB_SRC M/N En SB_SRC M/N Prog. Enable RW M/N Prog. Disabled M/N Prog. Enabled 0 Bit 3 S EL_OC_MODE readback OC MODE Select R PCIE Gen2 Mode PCIE Gen1 Mode Latch Bit 2 IO_VOUT2 IO Output Voltage Select (Most Significant B it) RW 1 Bit 1 IO_VOUT1 IO Output Voltage Select RW 0 Bit 0 IO_VOUT0 IO Output Voltage Select (Least Significant B it) RW 1 Bytes 13/14 are reserved SMBus Table:Test Mode Register Byte 15 Name Control Function Type 0 1 Default Bit 7 Test_Sel Sele cts Test Mode RW Normal mode All ouputs are REF/N 0 Bit 6 SB_S RC Source SB_S RC Source Sel ection RW SB_SRC PLL SRC PLL 1 Bit 5 ATIG PLL ATIG PLL DOC pin control RW DOC0 DOC1 0 Bit 4 CPU PLL CPU PLL DOC pin control RW DOC0 DOC1 0 Bit 3 SRC PLL SRC PLL DOC pin control RW DOC0 DOC1 0 Bit 2 ATIG PLL ATIG PLL DOC0 2 pin control RW Disable Enable 0 Bit 1 CPU PLL CPU PLL DOC0 2 pin control RW Disable Enable 0 Bit 0 SRC PLL SRC PLL DOC0 2 pin control RW Disable Enable 0 SMBus Table: CPU PLL Frequency Control Register Byte 16 Name Control Function Type 0 1 Default Bit 7 N Div2 N Divider Prog bit 2 RW X Bit 6 N Div1 N Divider Prog bit 1 RW X Bit 5 M Div5 RW X Bit 4 M Div4 RW X Bit 3 M Div3 RW X Bit 2 M Div2 RW X Bit 1 M Div1 RW X Bit 0 M Div0 RW X SMBus Table: CPU PLL Frequency Control Register Byte 17 Name Control Function Type 0 1 Default Bit 7 N Div10 RW X Bit 6 N Div9 RW X Bit 5 N Div8 RW X Bit 4 N Div7 RW X Bit 3 N Div6 RW X Bit 2 N Div5 RW X Bit 1 N Div4 RW X Bit 0 N Div3 RW X SMBus Table: SB_SRC PLL Spread Spectrum Control Register Byte 18 Name Control Function Type 0 1 Default Bit 7 SSP7 RW X Bit 6 SSP6 RW X Bit 5 SSP5 RW X Bit 4 SSP4 RW X Bit 3 SSP3 RW X Bit 2 SSP2 RW X Bit 1 SSP1 RW X Bit 0 SSP0 RW X SMBus Table: SB_SRC PLL Spread Spectrum Control Register Byte 19 Name Control Function Type 0 1 Default Bit 7 SSP15 RW X Bit 6 SSP14 RW X Bit 5 SSP13 RW X Bit 4 SSP12 RW X Bit 3 SSP11 RW X Bit 2 SSP10 RW X Bit 1 SSP9 RW X Bit 0 SSP8 RW X See Table 5: V_IO Sele ction (Default is 0.8V) The decimal representation of M and N Divider in Byte 16 and 17 will configure the VCO frequency. Default at power up = Byte 3 Rom table. See M/N Caculation Tables for VCO frequency formulas. M Divider Programming bits N Divider Programming b(10:3) The decimal representation of M and N Divider in Byte 16 and 17 will configure the VCO frequency. Default at power up = Byte 3 Rom table. See M/N Caculation Tables for VCO frequency formulas. Spread Spectrum P rogramming b(7:0) These bits set the SB_S RC spread pecentage.Please contact IDT for the appropriate values. Spread Spectrum P rogramming b(15:8) These bits set the SB_S RC spread pecentage.Please contact IDT for the appropriate values. |
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