9LPRS477D

PROGRAMMABLE SYSTEM CLOCK CHIP FOR ATI RD790-K8TM BASED SYSTEMS

IDT®

PROGRAMMABLE SYSTEM CLOCK CHIP FOR ATI RD790-K8TM BASED SYSTEMS

17

9LPRS477D

REV C 010715

Absolute Maximum Ratings

Stresses above the ratings listed below can cause permanent damage to the 9LPRS477D. These ratings, which are

standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any

other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute

maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over

the recommended operating temperature range.

Electrical Characteristics–Input/Supply/Common Output Parameters

P ARAMETE R

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

Notes

3 .3V Core Supply Voltage

VDDxxx

-3.3

GND + 3.9V

V

1

Storage Temperature

Ts

-

-65

150

° C

1

Ambient Operating Temp

Tambient

-

070

°C

1

Case Temperature

Tcase

-

115

°C

1

Input ESD protection HBM

ESD prot

-

2000

V

1

1Guaranteed by design and characterization, not 100% tested in production.

P ARAMETE R

SYMBOL

CONDITIONS*

MIN

TYP

MAX

UNITS

Notes

3 .3V Core Supply Voltage

VDDxxx

-

3.135

3.3

3.465

V

1

Input High Voltage

VIH

VDD = 3.3 V +/-5%

2

VDD + 0.3

V

1

Input Low Voltage

V

IL

VDD = 3.3 V +/-5%

V

SS - 0 .3

0.8

V

1

Input High Current

I

IH

V

IN = V DD

-5

5

uA

1

IIL1

VIN = 0 V; Inputs with no pull-up

resistors

-5

uA

1

I

IL2

VIN = 0 V ; Inputs with pull-up

resistors

-200

uA

1

Low Thresh old Input-

High Voltage

V IH_FS

VDD = 3.3 V +/-5%

0.7

VDD + 0.3

V

1

Low Thresh old Input-

Low Voltage

VIL_FS

VDD = 3.3 V +/-5%

VSS - 0 .3

0.35

V

1

Operating Current

I

DD3.3OP

all outputs driven

225

mA

1

Powerdown Current

I

DD3.3PD

all diff pairs low/low

12

mA

1

Input Frequency

Fi

VDD = 3.3 V +/-5%

14.31818

MHz

2

Pin Inductance

L pin

7nH

1

CIN

Logic Inputs

5

pF

1

C

OUT

Output pin capacitance

6

pF

1

C

INX

X1 & X 2 pins

5

pF

1

Clk Stabiliza tion

TSTAB

From VDD Power-Up or de-

assertion of PD to 1st cl ock

1.8

ms

1

Modulation Frequency

Triangular Modulation

30

33

kHz

1

Tdrive_PD

CPU output enable after

PD de-assertion

300

us

1

Tfall_ PD

PD fall time of

5

ns

1

Trise_PD

PD rise time of

5

ns

1

SMBus Voltage

VDDSMB

2.7

5.5

V

1

Low-level Output Voltage

V

OL SMB

@ I

PUL LUP

0.4

V

1

Current sinking at

V

OL = 0.4 V

I

PUL LU PSMB

46

mA

1

SMB CLK/SMBDAT

Clock/Data Rise Time

TRSMB

(Max VIL - 0.15) to

(Min V IH + 0.15)

1000

ns

1

SMB CLK/SMBDAT

Clock/Data Fall Time

TFSMB

(Min VIH + 0.15) to

(Max VIL - 0.15)

300

ns

1

*TA = 0 - 70°C; S upply Voltage VDD = 3.3 V +/-5%

1Guaranteed by design and characterization, not 100% tested in production.

Input L ow Current

Input Capacitance

2 Input frequ ency should be measured at the REF pin and tuned to ideal 14.31818MHz to meet ppm frequency accuracy on PLL outputs.