9LPRS477D

PROGRAMMABLE SYSTEM CLOCK CHIP FOR ATI RD790-K8TM BASED SYSTEMS

IDT®

PROGRAMMABLE SYSTEM CLOCK CHIP FOR ATI RD790-K8TM BASED SYSTEMS

19

9LPRS477D

REV C 010715

AC Electrical Characteristics–Low-Power DIF Outputs: SRC, SB_SRC, ATIG

Electrical Characteristics–Single-Ended HTT 66MHz Clock

P ARAMETE R

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS NOTES

Rising Edge Slew Rate

tSLR

Differential Measurement

0.6

4

V/ns

1,2

Falling Edge Slew Rate

t

FL R

Differential Measurement

0.6

4

V/ns

1,2

Slew Rate Variation

tSLVAR

Single-ended Measurement

20

%

1

Maximum Output Voltage

V

HIGH

Incl udes overshoot

1150

mV

1

Minimum Output Voltage

VLOW

Includes undershoot

-300

mV

1

Differential Voltage Swing

VSWING

Differential Measurement

300

mV

1

Crossing Point Voltage

VXABS

Single-ended Measurement

300

550

mV

1,3,4

Cro ssing Point Variation

V

XABSVAR

Single-ended Measurement

140

mV

1,3,5

Duty Cycle

D

CYC

Differential Measurement

45

55

%

1

SRC, SB_SRC, ATIG,

Jitter - Cycle to Cycle

SRCJC2C

Differential Measurement

125

ps

1

SRC[5:0] Skew

SRCSKEW

Differential Measurement

250

ps

1

SB _SRC[1:0] Skew

SRCSKEW

Differential Measurement

100

ps

1

ATIG[3:0] Skew

SRC

SKEW

Differential Measurement

100

ps

1

*TA = 0 - 70°C; S upply Voltage VDD = 3.3 V +/-5%, CL = 2pF with Rs = 0Ω (unless otherwise specified)

1Guaranteed by design and characterization, not 100% tested in production.

2 Slew rate measured through Vswing centered around differential zero

3 Vxabs is defined as the voltage where CLK = CLK#

4 Only applies to the differential rising edge (CLK rising and CLK# falling)

6 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz

5 Defined as the total variation of all crossing voltages of CLK rising and CLK# falling. Matching applies to rising edge rate of CLK and falling

edge of CLK#. It is measured using a +/-75mV window centered on the average cross point where CLK meets CLK#.

P ARAMETE R

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

Notes

Long Accuracy

ppm

see Tperiod min-max values

-300

300

ppm

1,2

33.33MHz output nominal

29.9910

30.0090

ns

2

33.33MHz output spread

29.9910

30.1598

ns

2

66.67MHz output nominal

14.9955

15.0045

ns

2

66.67MHz output spread

14.9955

15.0799

ns

2

Outp ut High Volta ge

V

OH

I

OH = -1 mA

2.4

V

1

Output Low Voltage

V

OL

I

OL = 1 mA

0.55

V

1

V OH @MIN = 1.0 V

-33

mA

1

VOH@ MAX = 3.135 V

-33

mA

1

VOL @ MIN = 1.95 V

30

mA

1

V

OL @ MAX = 0.4 V

38

mA

1

Edge Rate

Vt

Rising edge rate

1

4

V/ns

1

Edge Rate

Vt

Falling edge rate

1

4

V/ns

1

Rise Time

t

r1

V

OL = 0.4 V, VOH = 2. 4 V

0.5

2

ns

1

Fall Time

tf1

V OH = 2.4 V, V OL = 0.4 V

0.5

2

ns

1

Duty Cycle

dt1

VT = 1.5 V

45

55

%

1

Jitter, Cycle to cycle

t

j cyc-cyc

V

T = 1.5 V

180

ps

1

*TA = 0 - 70°C; S upply Voltage VDD = 3.3 V +/-5%, CL = 5pF with Rs = 33

Ω (unless otherwise specified)

1Guaranteed by design and characterization, not 100% tested in production.

2 All Long Term Accuracy and Clock Period specifications are guaranteed with the assumption that REF is at 14.31818MHz

Output Low Current

I

OL

PCI33 Clock period

Tperiod

HTT66 Clock period

Tperiod

Output High Current

IOH