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AT25QL641 Datasheet(PDF) 30 Page - Renesas Technology Corp |
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AT25QL641 Datasheet(HTML) 30 Page - Renesas Technology Corp |
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30 / 80 page ![]() DS-AT25QL641-130 Rev. G Page 30 Sep 14, 2022 © 2022 Renesas Electronics AT25QL641 Datasheet 8.11 Fast Read Dual Output (3Bh) By using two pins (I/O0 and I/O1, instead of just I/O0), The Fast Read Dual Output command allows data to be transferred from the AT25QL641 at twice the rate of standard SPI devices. The Fast Read Dual Output command is ideal for quickly downloading code from Flash to RAM upon power-up or for application that cache code- segments to RAM for execution. The Fast Read Dual Output command can operate at the highest possible frequency of FR (see Table 26, AC Electrical Characteristics). After the 24-bit address, this is accomplished by adding eight dummy clocks as shown in Figure 18. The dummy clocks allow the internal circuits additional time for setting up the initial address. During the dummy clocks, the data value on the SO pin is a don’t care. However, the I/O0 pin should be high-impedance prior to the falling edge of the first data out clock. Figure 18. Fast Read Dual Output Command (SPI Mode) SCK CS SI SO 1 0 234 6 579 810 28 23 22 21 3 2 1 0 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 High-Impedance 24-Bit Address Command 3Bh SCK CS SI SO High-Impedance Dummy Clocks Data Byte 1 Data Byte 2 75 3 1 64 2 0 75 3 1 64 2 0 |
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