12

ICSSSTUB32866B

Advance Information

1165A—3/21/07

2. Device standard (cont'd)

†

CK †

D1•D25 †

RST

DCS †

CSR †

CK †

Q1•Q25

PAR_IN †

PPO

QERR

tinact

tRPHL

RST to Q

tRPHL

RST to PPO

tRPLH

RST to QERR

H, L, or X

H or L

Figure 11 — Timing diagram for SSTU32866 used as a single device; C0=0, C1=0;

RST switches from H to L

After RST is switched from high to low, all data and clock unouts signals must be set and held at valid logic levels (not floating) for

a minimum time of t

max.

INACT