16

ICSSSTUB32866B

Advance Information

1165A—3/21/07

2. Device standard (cont'd)

‡

PAR_IN is driven from PPO of the first SSTU32866 device.

§

If the data is clocked in on the n clock pulse, the QERR# output signal will be generated on the n+2 clock pulse, and it will be valid on

the n+3 clock pulse.

CK

D1•D14 †

RST#

tsu

tpd

CK to PPO

th

tsu

th

tpdm , t pdmss

CK to Q

DCS#

CSR#

CK#

Q1•Q14

PAR_IN †‡

n

n + 1

n + 2

PPO

(not used)

n + 3

n + 4

tPHL

CK to QERR#

QERR# §

tPHL , t PLH

CK to QERR#

tact

H, L, or X

H or L

Data to QERR#

Latency

Figure 15 — Timing diagram for the second SSTU32866 (1:2 register-B configuration) device used in

pair; C0=1, C1=1; RST# switches from L to H

After RST# switched from low to high, all data and PAR_IN inputs signals must be set and held low for a minimum time of t

max, to avoid false error.

ACT

†