18

ICSSSTUB32866B

Advance Information

1165A—3/21/07

2. Device standard (cont'd)

CK

†

D1•D14 †

RST#

DCS# †

CSR# †

CK# †

Q1•Q14

PAR_IN †

PPO

(not used)

QERR#

tinact

tRPHL

RST# to Q

tRPHL

RST# to PPO

tRPLH

RST# to QERR#

H, L, or X

H or L

†

Figure 17 — Timing diagram for the second SSTU32866 (1:2 register-B configuration) device used in

pair; C0=1, C1=1; RST# switches from H to L

After RST# is switched from high to low, all data and clock input signals must be held at valid logic levels (not floating) for a

munimum time of t

max.

INACT