ISL70003ASEH datasheet(30/36 Pages) RENESAS

30 / 36 page

ISL70003ASEH

FN8746 Rev.4.01

Page 30 of 36

Dec 12, 2019

PCB Design

PCB design is critical to high frequency switching regulator

performance. Careful component placement and trace routing

are necessary to reduce voltage spikes and minimize

undesirable voltage drops. Selection of a suitable thermal

interface material is also required for optimum heat dissipation

and to provide lead strain relief.

Optimize load regulation by reducing noise from the power and

digital grounds into the analog ground by splitting ground into

three planes: analog, digital, and power. Bypass or ground pins

accordingly to their design preferred ground. See the “Pin

Descriptions” on page 5 and Figure 4 on page 8 for guidance.

Independently tie each of the analog and digital grounds to

power ground through a single trace in a low noise area.

PCB Plane Allocation

A minimum of four layers of two ounce copper are

recommended. Layer 2 should be a dedicated ground plane with

all critical component ground connections made with vias to this

layer. Layer 3 should be a dedicated power plane split between

the input and output power rails. Layers 1 and 4 should be used

primarily for signals but can also provide additional power and

ground islands as required.

PCB Component Placement

Place components as close as possible to the IC to minimize

stray inductance and resistance. Prioritize the placement of

bypass capacitors on the pins of the IC in the order shown: REF,

SS_CAP, AVDD, DVDD, PVINx (high-frequency capacitors), EN,

PGOOD, PVINx (bulk capacitors).

Locate the output voltage resistive divider as close as possible to

the FB pin of the IC. Connect the top leg of the divider directly to

the output of the inductor through a Kelvin trace and the bottom

leg of the divider directly to AGND pin. This AGND connection is

also a Kelvin trace connected to the closest ground to the

inductor output. Connect the junction of the resistive divider

directly to the FB pin.

Place a Schottky clamp diode as close as possible to the LXx and

PGNDx pins of the IC. A small series R-C snubber connected from

the LXx pins to the PGNDx pins may be used to damp

high-frequency ringing on the LXx pins, see Figure 60.

LX Connection

Use a small island of copper to connect the LXx pins of the IC to

the output inductor on Layers 1 and 4. Void the copper on

Layers 2 and 3 adjacent to the island to minimize capacitive

coupling to the power and ground planes. Place most of the

island on Layer 4 to minimize the amount of copper that must be

voided from the ground plane (Layer 2).

Keep all other signal traces as short as possible.

Lead Strain Relief

The package leads protrude from the bottom of the package and

the leads need forming to provide strain relief. On the heatsink

option of the package R64.C, the lead forming should be made

so that the bottom of the heatsink and the formed leads are

flush.

Heatsink Mounting Guidelines

The R64.C package option has a heatsink mounted on the

underside of the package. The following JESD-51x series

guidelines may be used to mount the package:

1. Place a thermal land on the PCB under the heatsink.

2. The land should be approximately the same size as to 1mm

larger than the 10.16x10.16mm heatsink.

3. Place an array of thermal vias below the thermal land.

- Via array size: ~9x9 = 81 thermal vias.

- Via diameter: ~0.3mm drill diameter with plated copper on

the inside of each via.

- Via pitch: ~1.2mm.

- Vias should drop to and contact as much metal area as

feasible to provide the best thermal path.

Heatsink Electrical Potential

The heatsink is connected to Pin 50 within the package, so the

PCB design and potential applied to Pin 50 defines the heatsink

potential.

Heatsink Mounting Materials

In the case of electrically conductive mounting methods

(conductive epoxy, solder, etc.) the thermal land, vias, and

connected plane(s) below must be the same potential as Pin 50.

In the case of electrically nonconductive mounting methods

(nonconductive epoxy), the heatsink and Pin 50 could have

different electrical potential than the thermal land, vias, and

connected plane(s) below.

FIGURE 60. SCHOTTKY DIODE AND R-C SNUBBER

COUT

LOUT

VOUT

LXx

ERROR

AMPLIFIER

PGNDx

CREF

REF

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