ISL70003ASEH datasheet(21/36 Pages) RENESAS

21 / 36 page

ISL70003ASEH

FN8746 Rev.4.01

Page 21 of 36

Dec 12, 2019

Equation 2 defines the relationship between the resistor divider,

sink current, and POR rising level (VPORR).

When the voltage at the POR pin reaches the enable threshold,

the IPOR current sink turns off.

With the part enabled and the IPOR current sink off, the falling level

(VPORF) is set by the resistor divider network and is defined by

Equation 3.

The difference between the POR rising and falling levels provides

adjustable hysteresis so that noise on VIN does not interfere with

the enabling or disabling of the regulator.

Soft-Start

The ISL70003ASEH soft-start function uses an internal current

source and an external capacitor to reduce stresses and surge

current during start-up.

When the POR and enable circuits are satisfied, the regulator

waits 32 clock cycles and then initiates a soft-start. Figure 47

shows that the soft-start circuit clamps the error amplifier

reference voltage to the voltage on an external soft-start

capacitor connected to the SS pin. The soft-start capacitor is

charged by an internal ISS current source. As the soft-start

capacitor is charged, the output voltage slowly ramps to the set

point determined by the reference voltage and the feedback

network. When the voltage on the SS pin is equal to the internal

reference voltage, the soft-start interval is complete. Following

the soft-start interval is a delay to power good being signaled.

The soft-start output ramp interval is defined in Equation 4 and is

adjustable from approximately 2ms to 200ms. The value of the

soft-start capacitor, CSS, should range from 82nF to 8.2µF,

inclusive. The peak inrush current can be computed from

Equation 5. Select a soft-start interval that is long enough to

ensure that the peak inrush current plus the peak output load

current does not exceed the overcurrent trip level of the regulator.

The soft-start capacitor is immediately discharged by a 3.0Ω



resistor whenever POR conditions are not met or EN is pulled low.

The soft-start discharge time is equal to 256 clock cycles.

Power-Good

A power-good indicator is the final step of initialization. After a

successful soft-start, the PGOOD pin releases and the voltage

rises with an external pull-up resistor. The power-good signal

transitions low immediately when the EN pin is pulled low.

The PGOOD pin is an open-drain, logic output and can be pulled

up to any voltage from 0V to 13.2V. The pull-up resistor should

have a nominal value from 1kΩ to 10kΩ. To mitigate SEE, bypass

the PGOOD pin to DGND with a 10nF ceramic capacitor.

Fault Monitoring and Protection

The ISL70003ASEH actively monitors the output voltage and

current to detect fault conditions. Fault conditions trigger

protective measures to prevent damage to the regulator and the

external load device. One common power-good indication signal

is provided for linking to external system monitors. The

schematic in Figure 48 on page 22 outlines the interaction

between the fault monitors and the power-good signal.

Undervoltage and Overvoltage Monitor

The power-good pin (PGOOD) is an open-drain, logic output which

indicates that the converter is operating properly and the output

voltage is within a set window. The Undervoltage (UV) and

FIGURE 46. POR CIRCUIT

POR

PVINx

VIN

POR

LOGIC

VIN

IPOR

POR

COMPARATOR

CPOR

VR = 0.6V

IPOR = 12µA

CPOR = 10nF

INT. REG

VPORR

VR 1

-------



IPOR R1



(EQ. 2)

VPORF

VR 1

-------



(EQ. 3)

tSS

CSS

VREF

ISS

---------------



(EQ. 4)

IINRUSH

COUT

VOUT

tSS

----------------



(EQ. 5)

FIGURE 47. SOFT-START CIRCUIT

VREF

PWM

LOGIC

ISS

ERROR

AMPLIFIER

VOUT

CSS

VREF = 0.6V

ISS = 23µA

RD = 2.2Ω

VREF

CREF

REF

ISL70003ASEH Datasheet(PDF) 21 Page - Renesas Technology Corp

ISL70003ASEH Datasheet(HTML) 21 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36

Datasheet Download

Link URL