STM32H7 datasheet(353/357 Pages) STMICROELECTRONICS

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DS12110 Rev 10

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STM32H742xI/G STM32H743xI/G

Revision history

356

24-Apr-2019

Updated Figure 1: STM32H742xI/G block diagram

Updated Figure 2: STM32H743xI/G block diagram

Updated Table 9: Pin/ball definition.

Updated Table 10 to Table 20 (alternate functions).

Updated Table 39: Peripheral current consumption in Run mode.

Updated Table 137: Peripheral current consumption in Run mode.

Updated Table 184: ADC characteristics.

Updated Table 185: Minimum sampling time vs RAIN.

Updated Table 186: ADC accuracy.

02-Mar-2021

Added reference to errata sheet ES0392 in Section 1: Introduction.

Added connection between SDMMC2 and D2-to-D3 AHB bus in Figure 4:

STM32H743xI/G bus matrix.

Updated Section 3.27: True random number generator (RNG).

Added Full-duplex mode in Section 3.33: Serial peripheral interfaces (SPI)/integrated

interchip sound interfaces (I2S).

In Table 2: STM32H742xI/G and STM32H743xI/G features and peripheral counts, split

number of ADC channels into Direct, Fast and Slow channels; and added number of

wakeup and tamper pins.

Updated J1 and F2 signals in Figure 12: TFBGA240+25 ballout

Section 6: Electrical characteristics (rev Y):

– Updated Section 6.2: Absolute maximum ratings introduction to device mission

profile.

– Added a 1 μF capacitor between VDD33USB and ground in Figure 15: Power supply

scheme.

– Power dissipation (PD) removed from Table 24: General operating conditions since

this parameter is redundant with

ΘJA thermal resistance.

– Table 53: Flash memory programming: removed reference to single bank

configuration in title and added tERASE128KB typical and maximum values.

– Added reference to AN4899 in Section 6.3.15: I/O port characteristics. Updated notes

in Table 64: Output timing characteristics (HSLV ON).

– Updated tsu(DV-CLKH)/th(DV-CLKH) and tsu(NWAIT-CLKH)/th(NWAIT-CLKH) in Table 74:

Synchronous multiplexed NOR/PSRAM read timings. Changed t(NWAIT-CLKH) to

tsu(NWAIT-CLKH) and updated tsu(DV-CLKH)/th(DV-CLKH) and tsu(NWAIT-CLKH)/th(NWAIT-CLKH)

in Table 76: Synchronous non-multiplexed NOR/PSRAM read timings. Updated

tsu(SDCLKH _Data) and th(SDCLKH _Data) in Table 80: SDRAM read timings and Table 81:

LPSDR SDRAM read timings.

– Updated ts(IN) and th(IN) in Table 84: QUADSPI characteristics in SDR mode and

tsr(IN)/tsf(IN) and thr(IN)/thf(IN) in Table 85: QUADSPI characteristics in DDR mode.

– Updated maximum sampling time (tS) value in Table 87: ADC characteristics.

Specified that Figure 40: ADC accuracy characteristics is an example for 12-bit

resolution.

– Updated DuCyCKOUT in Table 100: DFSDM measured timing - 1.62-3.6 V.

– Updated tsu(MI) and th(MI) minimum values in Table 106: SPI dynamic characteristics.

– Updated tISU, tIH, tISUDand tIHD in Table 110: Dynamic characteristics: SD / MMC

characteristics, VDD = 2.7 to 3.6 V

– Updated tISU, tIH in Table 111: Dynamic characteristics: eMMC characteristics,

VDD = 1.71 to 1.9 V.

– Updated DuCyCKOUT in Table 100: DFSDM measured timing - 1.62-3.6 V.

Table 231. Document revision history

Date

Revision

Changes

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