PIC18F6410ESLASHPTSQTP datasheet(218/404 Pages) MICROCHIP

218 / 404 page

PIC18F6310/6410/8310/8410

DS39635A-page 216

Preliminary

 2004 Microchip Technology Inc.

17.1.3

AUTO-BAUD RATE DETECT

The Enhanced USART module supports the automatic

detection and calibration of baud rate. This feature is

active only in Asynchronous mode and while the WUE

bit is clear.

The automatic baud rate measurement sequence

(Figure 17-1) begins whenever a Start bit is received

and the ABDEN bit is set. The calculation is

self-averaging.

In the Auto-Baud Rate Detect (ABD) mode, the clock to

the BRG is reversed. Rather than the BRG clocking the

incoming RX1 signal, the RX1 signal is timing the BRG.

In ABD mode, the internal Baud Rate Generator is

used as a counter to time the bit period of the incoming

serial byte stream.

Once the ABDEN bit is set, the state machine will clear

the BRG and look for a Start bit. The Auto-Baud Rate

Detect must receive a byte with the value, 55h (ASCII

“U”, which is also the LIN bus Sync character), in order

to calculate the proper bit rate. The measurement is

taken over both a low and a high bit time in order to

minimize any effects caused by asymmetry of the

incoming signal. After a Start bit, the SPBRG1 begins

counting up, using the preselected clock source on the

first rising edge of RX1. After eight bits on the RX1 pin

or the fifth rising edge, an accumulated value totalling

the

proper

BRG

period

left

the

SPBRGH1:SPBRG1 register pair. Once the 5th edge is

seen (this should correspond to the Stop bit), the

ABDEN bit is automatically cleared.

If a rollover of the BRG occurs (an overflow from FFFFh

to 0000h), the event is trapped by the ABDOVF status bit

(BAUDCON1<7>). It is set in hardware by BRG rollovers

and can be set or cleared by the user in software. ABD

mode remains active after rollover events and the

ABDEN bit remains set (Figure 17-2).

While calibrating the baud rate period, the BRG

registers are clocked at 1/8th the preconfigured clock

rate. Note that the BRG clock will be configured by the

BRG16 and BRGH bits. Independent of the BRG16 bit

setting, both the SPBRG1 and SPBRGH1 will be used

as a 16-bit counter. This allows the user to verify that

no carry occurred for 8-bit modes by checking for 00h

in the SPBRGH1 register. Refer to Table 17-4 for

counter clock rates to the BRG.

While the ABD sequence takes place, the EUSART

state machine is held in Idle. The RC1IF interrupt is set

once the fifth rising edge on RX1 is detected. The value

in the RCREG1 needs to be read to clear the RC1IF

interrupt. The contents

of RCREG1 should be

discarded.

TABLE 17-4:

BRG COUNTER CLOCK

RATES

17.1.3.1

ABD and EUSART Transmission

Since the BRG clock is reversed during ABD acquisi-

tion, the EUSART transmitter cannot be used during

ABD. This means that whenever the ABDEN bit is set,

TXREG1 cannot be written to. Users should also

ensure that ABDEN does not become set during a

transmit sequence. Failing to do this may result in

unpredictable EUSART operation.

Note 1: If the WUE bit is set with the ABDEN bit,

Auto-Baud Rate Detection will occur on

the byte following the Break character.

2: It is up to the user to determine that the

incoming character baud rate is within the

range of the selected BRG clock source.

Some combinations of oscillator frequency

and EUSART baud rates are not possible

due to bit error rates. Overall system timing

and communication baud rates must be

taken into consideration when using the

Auto-Baud Rate Detection feature.

BRG16

BRGH

BRG Counter Clock

FOSC/512

FOSC/128

FOSC/32

Note:

During the ABD sequence, SPBRG1 and

SPBRGH1 are both used as a 16-bit

counter, independent of the BRG16 setting.

PIC18F6410E/PTSQTP Datasheet(PDF) 218 Page - Microchip Technology

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