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PIC18F6410E/PTSQTP Datasheet(PDF) 93 Page - Microchip Technology

Part # PIC18F6410E/PTSQTP
Description  64/80-Pin Flash Microcontrollers with nanoWatt Technology
PDF  404 Pages
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Manufacturer  MICROCHIP [Microchip Technology]
Direct Link  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

PIC18F6410E/PTSQTP Datasheet(HTML) 93 Page - Microchip Technology

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 2004 Microchip Technology Inc.
Preliminary
DS39635A-page 91
PIC18F6310/6410/8310/8410
7.2
16-Bit Mode
In 16-bit mode, the external memory interface can be
connected to external memories in three different
configurations:
• 16-bit Byte Write
• 16-bit Word Write
• 16-bit Byte Select
The configuration to be used is determined by the
WM1:WM0
bits
in
the
MEMCON
register
(MEMCON<1:0>). These three different configurations
allow the designer maximum flexibility in using both
8-bit and 16-bit devices with 16-bit data.
For all 16-bit modes, the Address Latch Enable (ALE)
pin indicates that the address bits, A<15:0>, are avail-
able on the external memory interface bus. Following the
address latch, the Output Enable signal (OE) will enable
both bytes of program memory at once to form a 16-bit
instruction word. The Chip Enable signal (CE) is active
at any time that the microcontroller accesses external
memory, whether reading or writing; it is inactive
(asserted high) whenever the device is in Sleep mode.
In Byte Select mode, JEDEC standard Flash memories
will require BA0 for the byte address line and one I/O line
to select between Byte and Word mode. The other 16-bit
modes do not need BA0. JEDEC standard static RAM
memories will use the UB or LB signals for byte selection.
7.2.1
16-BIT BYTE WRITE MODE
Figure 7-1 shows an example of 16-bit Byte Write
mode for PIC18F8310/8410 devices. This mode is
used for two separate 8-bit memories connected for
16-bit operation. This generally includes basic EPROM
and Flash devices. It allows table writes to byte-wide
external memories.
During a TBLWT instruction cycle, the TABLAT data is
presented on the upper and lower bytes of the
AD15:AD0 bus. The appropriate WRH or WRL control
line is strobed on the LSb of the TBLPTR.
FIGURE 7-1:
16-BIT BYTE WRITE MODE EXAMPLE
AD<7:0>
A<19:16>
ALE
D<15:8>
373
A<x:0>
D<7:0>
A<19:0>
A<x:0>
D<7:0>
373
OE
WRH
OE
OE
WR(1)
WR(1)
CE
CE
Note 1: This signal only applies to table writes. See Section 6.1 “Table Reads and Table Writes”.
WRL
D<7:0>
(LSB)
(MSB)
PIC18F8410
D<7:0>
AD<15:8>
Address Bus
Data Bus
Control Lines
CE



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