PIC18F6410ESLASHPTSQTP datasheet(83/404 Pages) MICROCHIP

83 / 404 page

 2004 Microchip Technology Inc.

Preliminary

DS39635A-page 81

PIC18F6310/6410/8310/8410

5.5

Program Memory and the

Extended Instruction Set

The operation of program memory is unaffected by the

use of the extended instruction set.

Enabling the extended instruction set adds five

additional two-word commands to the existing PIC18

instruction set: ADDFSR, CALLW, MOVSF, MOVSS and

SUBFSR

. These instructions are executed as described

in Section 5.2.4 “Two-Word Instructions”.

5.6

Data Memory and the Extended

Instruction Set

Enabling the PIC18 extended instruction set (XINST

configuration bit = 1) significantly changes certain

aspects of data memory and its addressing. Specifi-

cally, the use of the Access Bank for many of the core

PIC18 instructions is different; this is due to the

introduction of a new addressing mode for the data

memory space. This mode also alters the behavior of

indirect addressing using FSR2 and its associated

operands.

What does not change is just as important. The size of

the data memory space is unchanged, as well as its

linear addressing. The SFR map remains the same.

Core PIC18 instructions can still operate in both Direct

and Indirect Addressing mode; inherent and literal

instructions do not change at all. Indirect addressing

with FSR0 and FSR1 also remain unchanged.

5.6.1

INDEXED ADDRESSING WITH

LITERAL OFFSET

Enabling the PIC18 extended instruction set changes

the behavior of indirect addressing using the FSR2

proper conditions, instructions that use the Access

Bank – that is, most bit-oriented and byte-oriented

instructions – can invoke a form of indexed addressing

using an offset specified in the instruction. This special

addressing mode is known as Indexed Addressing with

Literal Offset, or Indexed Literal Offset mode.

When

using

the

extended

instruction

set,

this

addressing mode requires the following:

• The use of the Access Bank is forced (‘a’ = 0);

and

• The file address argument is less than or equal to

5Fh.

Under these conditions, the file address of the

instruction is not interpreted as the lower byte of an

address (used with the BSR in direct addressing), or as

an 8-bit address in the Access Bank. Instead, the value

is interpreted as an offset value to an address pointer

specified by FSR2. The offset and the contents of

FSR2 are added to obtain the target address of the

operation.

5.6.2

INSTRUCTIONS AFFECTED BY

INDEXED LITERAL OFFSET MODE

Any of the core PIC18 instructions that can use direct

addressing are potentially affected by the Indexed

Literal Offset Addressing mode. This includes all

byte-oriented and bit-oriented instructions, or almost

one-half of the standard PIC18 instruction set. Instruc-

tions that only use Inherent or Literal Addressing

modes are unaffected.

Additionally, byte-oriented and bit-oriented instructions

are not affected if they use the Access Bank (Access

RAM bit is ‘1’), or include a file address of 60h or above.

Instructions meeting these criteria will continue to

execute as before. A comparison of the different possi-

ble addressing modes when the extended instruction

set is enabled is shown in Figure 5-9.

Those who desire to use byte-oriented or bit-oriented

instructions in the Indexed Literal Offset mode should

note the changes to assembler syntax for this mode.

This is described in more detail in Section 24.2.1

“Extended Instruction Syntax”.

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