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PIC18F6410E/PTSQTP Datasheet(PDF) 99 Page - Microchip Technology |
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PIC18F6410E/PTSQTP Datasheet(HTML) 99 Page - Microchip Technology |
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99 / 404 page ![]() 2004 Microchip Technology Inc. Preliminary DS39635A-page 97 PIC18F6310/6410/8310/8410 7.3.1 8-BIT MODE TIMING The presentation of control signals on the external memory bus is different for the various operating modes. Typical signal timing diagrams are shown in Figure 7-4 through Figure 7-6. FIGURE 7-8: EXTERNAL MEMORY BUS TIMING FOR TBLRD (MICROPROCESSOR MODE) FIGURE 7-9: EXTERNAL MEMORY BUS TIMING FOR TBLRD (EXTENDED MICROCONTROLLER MODE) Q2 Q1 Q3 Q4 Q2 Q1 Q3 Q4 Q4 Q4 Q4 Q4 ALE OE ABh WRL AD<7:0> BA0 33h Opcode Fetch MOVLW 55h from 007556h 92h 55h ‘1’ ‘1’ Table Read of 92h from 199E67h 1 TCY Wait Q2 Q1 Q3 Q4 Q2 Q1 Q3 Q4 Q2 Q1 Q3 Q4 Apparent Q Actual Q A<19:16> 0Ch 00h CE ‘0’ ‘0’ Memory Cycle Instruction Execution TBLRD Cycle 1 TBLRD Cycle 2 3Ah AD<15:8> CFh 0Eh Q2 Q1 Q3 Q4 Q2 Q1 Q3 Q4 Q2 Q1 Q3 Q4 A<19:16> ALE OE AD<7:0> CE Opcode Fetch Opcode Fetch Opcode Fetch TBLRD * TBLRD Cycle 1 ADDLW 55h from 000100h Q2 Q1 Q3 Q4 0Ch 33h TBLRD 92h from 199E67h 92h from 000104h Memory Cycle Instruction Execution INST(PC – 2) TBLRD Cycle 2 MOVLW 55h from 000102h MOVLW AD<15:8> CFh |
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