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PIC18F6410E/PTSQTP Datasheet(PDF) 123 Page - Microchip Technology |
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PIC18F6410E/PTSQTP Datasheet(HTML) 123 Page - Microchip Technology |
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123 / 404 page ![]() 2004 Microchip Technology Inc. Preliminary DS39635A-page 121 PIC18F6310/6410/8310/8410 TABLE 10-3: PORTB FUNCTIONS Pin Name Function TRIS Setting I/O I/O Type Description RB0/INT0 RB0 0 O DIG LATB<0> data output. 1 I TTL PORTB<0> data input; weak pull-up when RBPU bit is cleared. INT0 1 I ST External Interrupt 0 input. RB1/INT1 RB1 0 O DIG LATB<1> data output. 1 I TTL PORTB<1> data input; weak pull-up when RBPU bit is cleared. INT1 1 I ST External Interrupt 1 input. RB2/INT2 RB2 0 O DIG LATB<2> data output. 1 I TTL PORTB<2> data input; weak pull-up when RBPU bit is cleared. INT2 1 I ST External Interrupt 2 input. RB3/INT3/ CCP2 RB3 0 O DIG LATB<3> data output. 1 I TTL PORTB<3> data input; weak pull-up when RBPU bit is cleared. INT3 1 I ST External Interrupt 3 input. CCP2(1) 0 O DIG CCP2 compare output and CCP2 PWM output; takes priority over port data. 1 I ST CCP2 capture input. RB4/KBI0 RB4 0 O DIG LATB<4> data output. 1 I TTL PORTB<4> data input; weak pull-up when RBPU bit is cleared. KBI0 1 I TTL Interrupt on pin change. RB5/KBI1 RB5 0 O DIG LATB<5> data output 1 I TTL PORTB<5> data input; weak pull-up when RBPU bit is cleared. KBI1 1 I TTL Interrupt on pin change. RB6/KBI2/PGC RB6 0 O DIG LATB<6> data output 1 I TTL PORTB<6> data input; weak pull-up when RBPU bit is cleared. KBI2 1 I TTL Interrupt on pin change. PGC x I ST Serial execution (ICSP™) clock input for ICSP and ICD operation(2). RB7/KBI3/PGD RB7 0 O DIG LATB<7> data output. 1 I TTL PORTB<7> data input; weak pull-up when RBPU bit is cleared. KBI3 1 I TTL Interrupt on pin change. PGD x O DIG Serial execution data output for ICSP and ICD operation(2). x I ST Serial execution data input for ICSP and ICD operation(2). Legend: PWR = Power Supply, O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input, TTL = TTL Buffer Input, x = Don’t care (TRIS bit does not affect port direction or is overridden for this option). Note 1: Alternate assignment for CCP2 when the CCP2MX configuration bit is cleared (Microprocessor, Extended Microcontroller and Microcontroller with Boot Block modes, 80-pin devices only). Default assignment is RC1. 2: All other pin functions are disabled when ICSP or ICD operations are enabled. |
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