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UPD161401W/P Datasheet(PDF) 87 Page - Renesas Technology Corp |
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UPD161401W/P Datasheet(HTML) 87 Page - Renesas Technology Corp |
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87 / 126 page ![]() Data Sheet S15726EJ2V0DS 85 µµµµPD161401 6.33 Reverse Start Line Address Register (R48) The reverse start line address register specifies start line address of the display RAM the CPU accesses for reverse display. The range of the reverse lines is determined by this register and the reverse end line address register. RS D7 D6 D5 D4 D3 D2 D1 D0 1 IVS6 IVS5 IVS4 IVS3 IVS2 IVS1 IVS0 IVS6 to IVS0 Sets a start line address. Caution Make sure that IVS [6:0] ≤≤≤≤ 4FH. If 4FH is exceeded, operation is not guaranteed. Default value (default value of reset command) D7 D6 D5 D4 D3 D2 D1 D0 Note 0000000 Note 0 or 1 6.34 Reverse End Line Address Register (R49) The reverse end line address register specifies the end line address of the display RAM the CPU accesses for reverse display. The range of the reverse lines is determined by this register and the reverse start line address register. RS D7 D6 D5 D4 D3 D2 D1 D0 Setting 1 IVE6 IVE5 IVE4 IVE3 IVE2 IVE1 IVE0 IVE6 to IVE0 Sets an end line address. Caution Make sure that IVE [6:0] ≤≤≤≤ 4FH. If 4FH is exceeded, operation is not guaranteed. Default value (default value of reset command) D7 D6 D5 D4 D3 D2 D1 D0 Note 0000000 Note 0 or 1 |
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