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PSD835G2 Datasheet(PDF) 54 Page - STMicroelectronics |
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PSD835G2 Datasheet(HTML) 54 Page - STMicroelectronics |
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54 / 102 page  PSD835G2 54/102 80C251 The Intel 80C251 MCU features a user-config- urable bus interface with four possible bus config- urations, as shown in Table 33. The first configuration is 80C31 compatible, and the bus interface to the PSD is identical to that shown in Figure 22., page 53. The second and third configurations have the same bus connection as shown in Table 34., page 55. There is only one Read Strobe (PSEN) connected to CNTL1 on the PSD. The A16 connection to PA0 allows for a larg- er address input to the PSD. The fourth configura- tion is shown in Figure 23., page 56. Read Strobe (RD) is connected to CNTL1 and Program Select Enable (PSEN) is connected to CNTL2. The 80C251 has two major operating modes: Page mode and Non-page mode. In Non-page mode, the data is multiplexed with the lower ad- dress byte, and Address Strobe (ALE/AS, PD0) is active in every bus cycle. In Page mode, data (D7- D0) is multiplexed with address (A15-A8). In a bus cycle where there is a Page hit, Address Strobe (ALE/AS, PD0) is not active and only addresses (A7-A0) are changing. The PSD supports both modes. In Page Mode, the PSD bus timing is iden- tical to Non-Page Mode except the address hold time and setup time with respect to Address Strobe (ALE/AS, PD0) is not required. The PSD access time is measured from address (A7-A0) valid to data in valid. Table 33. 80C251 Configurations Configuration 80C251 READ/WRITE Pins Connecting to PSD Pins Page Mode 1 WR RD PSEN CNTL0 CNTL1 CNTL2 Non-Page Mode, 80C31 compatible A7-A0 multiplex with D7-D0 2 WR PSEN only CNTL0 CNTL1 Non-Page Mode A7-A0 multiplex with D7-D0 3 WR PSEN only CNTL0 CNTL1 Page Mode A15-A8 multiplex with D7-D0 4 WR RD PSEN CNTL0 CNTL1 CNTL2 Page Mode A15-A8 multiplex with D7-D0 |
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