PSD835G2 datasheet(68/102 Pages) STMICROELECTRONICS

68 / 102 page

PSD835G2

68/102

Port E – Functionality and Structure

Port E can be configured to perform one or more

of the following functions:

–

MCU I/O Mode

–

In-System Programming – JTAG port can be

enabled for programming/erase of the PSD

device. Refer to PROGRAMMING IN-CIR-

CUIT USING THE JTAG/ISP

INTERFACE, page 76 for more information.

–

Open Drain – Port E pins can be configured in

Open Drain Mode.

–

Battery Backup features – PE6 can be

configured as a Battery Input (VSTBY) pin. PE7

can be configured as a Battery On Indicator

output pin, indicating when VCC is less than

VBAT.

–

Latched Address Output – Provided latched

address (A7-A0) output.

Port F – Functionality and Structure

Port F can be configured to perform one or more

of the following functions:

–

MCU I/O Mode

–

CPLD Output – External Chip Select ECS7-

ECS0 can be connected to Port F (or Port C).

–

CPLD Input – as direct input of the CPLD

array.

–

Address In – addition high address inputs.

Direct input to the CPLD array, no Input

Macrocell (IMC) latching is available.

–

Latched Address Out – Provide latched

address out per Table 47., page 75.

–

Slew Rate – pins can be set up for fast slew

rate.

–

Data Port – connected to D7-D0 when Port F

is configured as Data Port for a non-

multiplexed bus.

–

Peripheral I/O Mode.

Port G – Functionality and Structure

Port G can be configured to perform one or more

of the following functions:

–

MCU I/O Mode

–

Latched Address Out – Provide latched

address out per Table 47., page 75.

–

Open Drain – pins can be configured in Open

Drain Mode.

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