PSD835G2 datasheet(66/102 Pages) STMICROELECTRONICS

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PSD835G2

66/102

Input Macrocells (IMC)

The Input Macrocells (IMC) can be used to latch or

store external inputs. The outputs of the Input

Macrocells (IMC) are routed to the PLD input bus,

and can be read by the MCU. See PLDs, page 38.

Enable Out

The Enable Out register can be read by the MCU.

It contains the output enable values for a given

port. A ‘1’ indicates the driver is in output mode. A

‘0’ indicates the driver is in tri-state and the pin is

in input mode.

Ports A,B and C – Functionality and Structure

Ports A and B have similar functionality and struc-

ture, as shown in Figure 28.

The two ports can be configured to perform one or

more of the following functions:

–

MCU I/O Mode

–

CPLD Output – Macrocells McellA7-McellA0

can be connected to Port A, McellB7-McellB0

can be connected to Port B, External Chip

Select ECS7-ECS0 can be connected to Port

–

CPLD Input – Via the Input Macrocells (IMC).

–

Address In – Additional high address inputs

using the Input Macrocells (IMC).

–

Open Drain/Slew Rate – pins PC7-PC0 can be

configured to fast slew rate, pins PA7-PA0 and

PB7-PB0 can be configured to Open Drain

Mode.

Figure 28. Port A, B and C Structure

DATA OUT

REG.

MCELLA7-MCELLA0 (PORT A)

MCELLB7-MCELLB0 (PORT B)

EXT.CS (PORT C)

ENABLE PRODUCT TERM (.OE)

READ MUX

CPLD - INPUT

DIR REG.

INPUT

MACROCELL

ENABLE OUT

DATA IN

OUTPUT

SELECT

OUTPUT

MUX

PORT PIN

DATA OUT

AI02887b

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