PSD835G2 datasheet(64/102 Pages) STMICROELECTRONICS

64 / 102 page

PSD835G2

64/102

JTAG In-System Programming (ISP)

Port E is JTAG compliant, and can be used for In-

System Programming (ISP). You can multiplex

JTAG operations with other functions on Port E

because In-System Programming (ISP) is not per-

formed in normal Operating mode. For more infor-

mation on the JTAG Port, see PROGRAMMING

IN-CIRCUIT

USING

THE

JTAG/ISP

INTERFACE, page 76.

Port Configuration Registers (PCR)

Each Port has a set of Port Configuration Regis-

ters (PCR) used for configuration. The contents of

the registers can be accessed by the MCU through

normal READ/WRITE bus cycles at the addresses

given in Table 5., page 19. The addresses in Ta-

ble 5 are the offsets in hexadecimal from the base

of the CSIOP register.

The pins of a port are individually configurable and

each bit in the register controls its respective pin.

For example, Bit 0 in a register refers to Bit 0 of its

port. The three Port Configuration Registers

(PCR), shown in Table 38, are used for setting the

Port configurations. The default Power-up state for

each register in Table 38 is 00h.

Control Register

Any bit reset to ’0’ in the Control Register sets the

corresponding port pin to MCU I/O Mode, and a ’1’

sets it to Address Out Mode. The default mode is

MCU I/O. Only Ports E, F and G have an associat-

ed Control Register.

Direction Register

The Direction Register, in conjunction with the out-

put enable (except for Port D), controls the direc-

tion of data flow in the I/O Ports. Any bit set to ’1’

in the Direction Register causes the correspond-

ing pin to be an output, and any bit set to ’0’ causes

it to be an input. The default mode for all port pins

is input.

Figure 28., page 66 and Figure 29., page 67 show

the Port Architecture diagrams for Ports A/B/C and

E/F/G, respectively. The direction of data flow for

Ports A, B, C and F are controlled not only by the

direction register, but also by the output enable

product term from the PLD AND Array. If the out-

put enable product term is not active, the Direction

An example of a configuration for a Port with the

three least significant bits set to output and the re-

mainder set to input is shown in Table 41. Since

Port D only contains four pins (shown in Figure

29., page 67), the Direction Register for Port D

has only the four least significant bits active.

Drive Select Register

The Drive Select Register configures the pin driver

as Open Drain or CMOS for some port pins, and

controls the slew rate for the other port pins. An

external pull-up resistor should be used for pins

configured as Open Drain.

A pin can be configured as Open Drain if its corre-

sponding bit in the Drive Select Register is set to a

'1.' The default pin drive is CMOS.

Note that the slew rate is a measurement of the

rise and fall times of an output. A higher slew rate

means a faster output response and may create

more electrical noise. A pin operates at a high slew

rate when the corresponding bit in the Drive Reg-

ister is set to '1.' The default rate is slow slew.

Table 42., page 65 shows the Drive Register for

Ports A, B, C, D, E and F. It summarizes which

pins can be configured as Open Drain outputs and

which pins the slew rate can be set for.

Table 38. Port Configuration Registers (PCR)

Note: 1. See Table 42., page 65 for Drive Register bit definition.

Table 39. Port Pin Direction Control, Output

Enable P.T. Not Defined

Table 40. Port Pin Direction Control, Output

Enable P.T. Defined

Table 41. Port Direction Assignment Example

Port

MCU Access

Control

E, F, G

WRITE/READ

Direction

A,B,C,D, E, F, G

WRITE/READ

Drive Select1

A,B,C,D, E, F, G

WRITE/READ

Direction Register Bit

Port Pin Mode

Input

Output

Direction

Output Enable

P.T.

Port Pin Mode

Input

Output

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

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