PSD835G2 datasheet(101/102 Pages) STMICROELECTRONICS

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PSD835G2

REVISION HISTORY

Table 74. Document Revision History

Date

Version

Description of Revision

01-Mar-2000

1.0

PSD835G2: Document written in the WSI format. Initial release.

30-Nov-2000

1.1

Turbo Off changed from +10 to +12 in Table 58, CPLD Combinatorial Timing, Table 59,

CPLD Macrocell Synchronous Clock Mode Timing, Table 60, CPLD Macrocell

Asynchronous Clock Mode Timing, Table 61, Input Macrocell Timing, Table 62, Read

Timing, Table 64, Port F Peripheral Data Mode Read Timing.

tCO max for 70ns speed class changed from 13 to 15 in Table 59.

tHA min and tCLA min for 70ns speed class changed from 5 to 7 and 9 to 12, respectively

and tCLA min for 90ns speed class changed from 12 to 15 in Table 60.

tLXAX min changed for 70ns speed class changed from 5 to 7 in Table 62.

tLXAX min changed for 70ns speed class changed from 5 to 7, tDVWH min for 70ns speed

class changed from 12 to 25, tWLWH min for 70ns speed class changed from 25 to 28 in

Table 63.

31-Jan-2002

1.2

PSD835G2: Configurable Memory System on a Chip for 8-bit Microcontrollers.

Front page and back two pages in ST format added to the PDF file.

Any references to Waferscale, WSI, EasyFLASH and PSDsoft 2000 updated to ST, ST,

Flash+PSD and PSDsoft.

11-Sep-2002

2.0

Document reformatted. No parameters changed.

03-Mar-04

3.0

Document reformatted; mechanical dimensions corrected (Table 71)

PSD835G2 Datasheet(PDF) 101 Page - STMicroelectronics