ADFS7124-8BBCPZ datasheet(59/93 Pages) AD

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Data Sheet

ADFS7124-8

DIGITAL FILTER

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Rev. 0 | 59 of 93

settling time when switching between channels for a sample of

FS[10:0].

When selecting another channel, the ADFS7124-8 allows the com-

plete settling time to generate the first conversion after the channel

change. Therefore, the ADC automatically operates in the zero

latency mode when several channels are enabled (setting the

SINGLE_CYCLE bit has no benefits).

When the analog input is constant or a channel change occurs,

valid conversions are available at a near constant output data rate.

When conversions are being performed on a single channel and

a step change occurs on the analog input, the ADC continues to

output fully settled conversions if the step change is synchronized

with the conversion process. If the step change is asynchronous,

one conversion is output from the ADC that is not completely

settled (see Figure 92).

ANALOG

INPUT

ADC

OUTPUT

FULLY

SETTLED

fADC

Figure 92. Sinc3 Zero Latency Operation

Table 58. Examples of Output Data Rates and the Corresponding Settling

Times for the Sinc3 Filter (Zero Latency)

Power Mode

FS[10:0]

Output Data Rate

(SPS)

Settling Time

(ms)

Full Power (fCLK =

614.4 kHz)

1920

3.33

300.15

384

16.67

60.15

320

50.15

Mid Power (fCLK =

153.6 kHz)

480

3.33

300.61

16.67

60.61

50.61

Low Power (fCLK =

76.8 kHz)

240

3.33

301.22

16.67

61.22

51.22

Sequencer

The description in the Sinc3 Filter section is valid when manually

switching channels, for example, writing to the device to change

channels. When multiple channels are enabled, the on-chip se-

quencer is automatically used; the device automatically sequences

between all enabled channels. In this case, the first conversion

takes the complete settling time, as listed in Table 57. For all

subsequent conversions, the time needed for each conversion is

also the settling time, but the dead time is reduced to:

►

30 when the old channel and new channel both have an FS[10:0]

> 1 or FS[10:0] = 1.

►

−4 when the old channel has an FS[10:0] > 1 and the new

channel has an FS[10:0] = 1.

►

64 when the old channel has an FS[10:0] = 1 and the new

channel has an FS[10:0] > 1.

Sinc3 50 Hz and 60 Hz Rejection

Figure 93 shows the frequency response of the sinc3 filter when

the output data rate is programmed to 50 SPS and zero latency is

disabled. For the same configuration but with zero latency enabled,

the filter response remains the same but the output data rate is

16.67 SPS. The sinc3 filter gives 50 Hz ± 1 Hz rejection of 95 dB

minimum for a stable controller clock.

–120

–110

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

100

125

150

FREQUENCY (Hz)

Figure 93. Sinc3 Filter Response (50 SPS Output Data Rate, Zero Latency

Disabled or 16.67 SPS Output Data Rate, Zero Latency Enabled)

Figure 94 shows the frequency response of the sinc3 filter when

the output data rate is programmed to 60 SPS and zero latency is

disabled. For the same configuration but with zero latency enabled,

the filter response remains the same but the output data rate is 20

SPS. The sinc3 filter has rejection of 95 dB minimum at 60 Hz ± 1

Hz, assuming a stable controller clock.

–120

–110

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

120

150

FREQUENCY (Hz)

Figure 94. Sinc3 Filter Response (60 SPS Output Data Rate, Zero Latency

Disabled or 20 SPS Output Data Rate, Zero Latency Enabled)

ADFS7124-8BBCPZ Datasheet(PDF) 59 Page - Analog Devices

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