ADFS7124-8BBCPZ datasheet(89/93 Pages) AD

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Data Sheet

ADFS7124-8

ON-CHIP REGISTERS

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Rev. 0 | 89 of 93

Table 73. Channel Register Bit Descriptions

Bits

Bit Name

Description

Enable

Channel enable bit. Setting this bit enables the device channel for the conversion sequence. By default, only the enable bit for Channel 0

is set. The order of conversions starts with the lowest enabled channel, then cycles through successively higher channel numbers, before

wrapping around to the lowest channel again.

When the ADC writes a result for a particular channel, the four LSBs of the status register are set to the channel number, 0 to 15. This allows

the channel the data corresponds to be identified. When the DATA_STATUS bit in the ADC_CONTROL register is set, the contents of the

status register are appended to each conversion when it is read. Use this function when several channels are enabled to determine to which

channel the conversion value read corresponds.

14:12

Setup

Setup select. These bits identify which of the eight setups are used to configure the ADC for this channel. A setup comprises a set of four

registers: analog configuration, output data rate/filter selection, offset register, and gain register. All channels can use the same setup, in

which case the same 3-bit value must be written to these bits on all active channels. Alternatively, up to eight channels can be configured

differently.

11:10

These bits must be programmed with a Logic 0 for correct operation.

9:5

AINP[4:0]

Positive analog input AINP input select. These bits select which of the analog inputs is connected to the positive input for this channel.

00000 = AIN0 (default).

00001 = AIN1.

00010 = AIN2.

00011 = AIN3.

00100 = AIN4.

00101 = AIN5.

00110 = AIN6.

00111 = AIN7.

01000 = AIN8.

01001 = AIN9.

01010 = AIN10.

01011 = AIN11.

01100 = AIN12.

01101 = AIN13.

01110 = AIN14.

01111 = AIN15.

10000 = temperature sensor.

10001 = AVSS.

10010 = internal reference.

10011 = DGND.

10100 = (AVDD − AVSS)/6+. Use in conjunction with (AVDD − AVSS)/6− to monitor supply AVDD − AVSS.

10101 = (AVDD − AVSS)/6−. Use in conjunction with (AVDD − AVSS)/6+ to monitor supply AVDD − AVSS.

10110 = (IOVDD − DGND)/6+. Use in conjunction with (IOVDD − DGND)/6− to monitor IOVDD − DGND.

10111 = (IOVDD − DGND)/6−. Use in conjunction with (IOVDD − DGND)/6+ to monitor IOVDD − DGND.

11000 = (ALDO − AVSS)/6+. Use in conjunction with (ALDO − AVSS)/6− to monitor the analog LDO.

11001 = (ALDO − AVSS)/6−. Use in conjunction with (ALDO − AVSS)/6+ to monitor the analog LDO.

11010 = (DLDO − DGND)/6+. Use in conjunction with (DLDO − DGND)/6− to monitor the digital LDO.

11011 = (DLDO − DGND)/6−. Use in conjunction with (DLDO − DGND)/6+ to monitor the digital LDO.

11100 = V_20MV_P. Use in conjunction with V_20MV_M to apply a 20 mV p-p signal to the ADC.

11101 = V_20MV_M. Use in conjunction with V_20MV_P to apply a 20 mV p-p signal to the ADC.

11110 = Reserved.

11111 = Reserved.

4:0

AINM[4:0]

Negative analog input AINM input select. These bits select which of the analog inputs is connected to the negative input for this channel.

00000 = AIN0.

00001 = AIN1 (default).

00010 = AIN2.

ADFS7124-8BBCPZ Datasheet(PDF) 89 Page - Analog Devices

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