ADFS7124-8BBCPZ datasheet(9/93 Pages) AD

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Data Sheet

ADFS7124-8

SPECIFICATIONS

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Rev. 0 | 9 of 93

Table 2. Specifications (Continued)

Parameter1

Min

Typ

Max

Unit

Test Conditions/Comments

IAVDD Increase per Reference Buffer2

120

µA

All gains

IAVDD Increase

Due to Internal Reference2

µA

Independent of power mode; the reference

buffers are not required when using this

reference

Due to VBIAS2

µA

Independent of power mode

Due to Diagnostics2

µA

IIOVDD

Low Power Mode

µA

Mid Power Mode

µA

Full Power Mode

µA

POWER-DOWN CURRENTS13

Independent of power mode

Standby Current

IAVDD

µA

LDOs on only

IIOVDD

µA

Power-Down Current

IAVDD

µA

IIOVDD

µA

1 Temperature range = −40°C to +125°C.

2 These specifications are not production tested but are supported by characterization data at the initial product release.

3 FS is the decimal equivalent of the FS[10:0] bits in the filter registers.

4 The nonlinearity is production tested in full power mode. For the other power modes, this specification is supported by characterization data at the initial product release.

5 Following a system or internal zero-scale calibration, the offset error is in the order of the noise for the programmed gain and output data rate selected. A system full- scale

calibration reduces the gain error to the order of the noise for the programmed gain and output data rate.

6 Recalibration at any temperature removes these errors.

7 Gain error applies to both positive and negative full-scale. A factory calibration is performed at gain = 1, TA = 25°C.

8 When gain > 1, the common-mode voltage is between (AVSS + 0.1 + 0.5/gain) and (AVDD − 0.1 − 0.5/gain).

9 Specification is for a wider common-mode voltage between (AVSS − 0.05 + 0.5/gain) and (AVDD − 0.1 − 0.5/gain).

10 REJ60 is a bit in the filter registers. When the first notch of the sinc filter is at 50 Hz, a notch is placed at 60 Hz when REJ60 is set to 1. This gives simultaneous 50 Hz and

60 Hz rejection.

11 When the gain is greater than 1, the analog input buffers are enabled automatically. The buffers can only be disabled when the gain equals 1.

12 When VREF = (AVDD − AVSS), the typical differential input equals 0.92 × VREF/gain for the low and mid power modes and 0.86 × VREF/gain for full power mode when gain >

13 The digital inputs are equal to IOVDD or DGND with excitation currents and bias voltage generator disabled.

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