ADFS7124-8BBCPZ datasheet(80/93 Pages) AD

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Data Sheet

ADFS7124-8

ON-CHIP REGISTERS

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Rev. 0 | 80 of 93

Table 63. Register Summary (Continued)

Addr. Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reset

0x31

0x38

GAIN_0 to

GAIN_7

Gain [23:16]

0x5XXXX

Gain [15:8]

Gain [7:0]

1 CHANNEL_0 is reset to 0x8001. All other channels are reset to 0x0001.

COMMUNICATIONS REGISTER

RS[5:0] = 0, 0, 0, 0, 0, 0

The communications register is an 8-bit, write only register. All communications to the device must start with a write operation to the

communications register. The data written to the communications register determines whether the next operation is a read or write operation,

and to which register this operation takes place, the RS[5:0] bits selecting the register to be accessed.

For read or write operations, after the subsequent read or write operation to the selected register is complete, the interface returns to where it

expects a write operation to the communications register. This is the default state of the interface and, on power-up or after a reset, the ADC is

in this default state waiting for a write operation to the communications register.

In situations where the interface sequence is lost, a write operation of at least 64 serial clock cycles with DIN high returns the ADC to this

default state by resetting the entire device. Table 64 outlines the bit designations for the communications register. Bit 7 denotes the first bit of

the data stream.

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

WEN (0)

R/W (0)

RS[5:0] (0)

Table 64. Communications Register Bit Descriptions

Bits

Bit Name

Description

WEN

Write enable bit. A 0 must be written to this bit so that the write to the communications register actually occurs. If a 1 is the first bit written, the

device does not clock on to subsequent bits in the register. It stays at this bit location until a 0 is written to this bit. As soon as a 0 is written to

the WEN bit, the next seven bits are loaded to the communications register.

R/W

A 0 in this bit location indicates that the next operation is a write to a specified register. A 1 in this position indicates that the next operation is a

read from the designated register.

5:0

RS[5:0]

Register address bits. These address bits select which registers of the ADC are being selected during this serial interface communication. See

Table 63.

STATUS REGISTER

RS[5:0] = 0, 0, 0, 0, 0, 0

Power-On/Reset = 0x00

The status register is an 8-bit, read only register. To access the ADC status register, write to the communications register, select the next

operation to be read, and set the register address bits RS[5:0] to 0.

Table 65 outlines the bit designations for the status register. Bit 7 denotes the first bit of the data stream. The number in parentheses indicates

the power-on/reset default status of that bit.

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

RDY (0)

ERROR_FLAG (0)

0 (0)

POR_FLAG (0)

CH_ACTIVE (0)

Table 65. Status Register Bit Descriptions

Bits

Bit Name

Description

RDY

Ready bit for the ADC. This bit is cleared when data is written to the ADC data register. The RDY bit is set automatically after the ADC data

register is read or a period of time before the data register is updated with a new conversion result to indicate not to read the conversion

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