ATMEGA406_0607 datasheet(71/263 Pages) ATMEL

71 / 263 page

2548E–AVR–07/06

ATmega406

• TMS/PCINT10 – Port B, Bit 2

TMS, JTAG Test Mode Select: This pin is used for navigating through the TAP-controller state

machine. When the JTAG interface is enabled, this pin can not be used as an I/O pin.

PCINT10, Pin Change Interrupt Source 10. The PB2 pin can serve as external interrupt source

to the MCU.

• TDI/PCINT9 – Port B, Bit 1

TDI, JTAG Test Data Input: Serial input data to be shifted in the Instruction Register or Data

PCINT9, Pin Change Interrupt Source 9. The PB1 pin can serve as external interrupt source to

the MCU.

• TDO/PCINT8 – Port B, Bit 0

TDO, JTAG Test Data Output: Serial output data from Instruction Register or Data Register.

When the JTAG Interface is enabled, this pin can not be used as an I/O pin.

PCINT8, Pin Change Interrupt Source 8. The PB0 pin can serve as external interrupt source to

the MCU.

Table 13-7 and Table 13-8 relate the alternate functions of Port B to the overriding signals

shown in Figure 13-5 on page 66.

Table 13-7.

Overriding Signals for Alternate Functions in PB7:PB4

Signal Name

PB7/OCOB/

PCINT15

PB6/OCOA/

PCINT14

PB5/

PCINT13

PB4/

PCINT12

PUOE

000

PUOV

000

DDOE

DDOV

PVOE

OC0B Enable

OC0A Enable

PVOV

OC0B

OC0A

PTOE

–

–––

DIEOE

000

DIEOV

000

PCINT15 INPUT

PCINT14 INPUT

PCINT13 INPUT

PCINT12 INPUT

AIO

–

–––

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