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ATMEGA406_0607 Datasheet(PDF) 52 Page - ATMEL Corporation |
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ATMEGA406_0607 Datasheet(HTML) 52 Page - ATMEL Corporation |
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52 / 263 page ![]() 52 2548E–AVR–07/06 ATmega406 Vectors are not used, and regular program code can be placed at these locations. This is also the case if the Reset Vector is in the Application section while the Interrupt Vectors are in the Boot section or vice versa. Note: 1. The Boot Reset Address is shown in Table 27-7 on page 193. For the BOOTRST Fuse “1” means unprogrammed while “0” means programmed. The most typical and general program setup for the Reset and Interrupt Vector Addresses in ATmega406 is: Table 11-2. Reset and Interrupt Vectors Placement (1) BOOTRST IVSEL Reset Address Interrupt Vectors Start Address 1 0 0x0000 0x0002 1 1 0x0000 Boot Reset Address + 0x0002 0 0 Boot Reset Address 0x0002 0 1 Boot Reset Address Boot Reset Address + 0x0002 Address Labels Code Comments 0x0000 jmp RESET ; Reset Handler 0x0002 jmp BPINT ; Battery Protection Interrupt Handler 0x0004 jmp EXT_INT0 ; External Interrupt Request 0 Handler 0x0006 jmp EXT_INT1 ; External Interrupt Request 1 Handler 0x0008 jmp EXT_INT2 ; External Interrupt Request 2 Handler 0x000A jmp EXT_INT3 ; External Interrupt Request 3 Handler 0x000C jmp PCINT0 ; Pin Change Interrupt 0 Handler 0x000E jmp PCINT1 ; Pin Change Interrupt 1 Handler 0x0010 jmp WDT ; Watchdog Time-out Interrupt 0x0012 jmp WAKE_UP ; Wake-up Timer Overflow 0x0014 jmp TIM1_COMP ; Timer1 Compare Handler 0x0016 jmp TIM1_OVF ; Timer1 Overflow Handler 0X0018 jmp TIM0_COMPA ; Timer0 CompareA Handler 0x001A jmp TIM0_COMPB ; Timer0 CompareB Handler 0x001C jmp TIM0_OVF ; Timer0 Overflow Handler 0x001E jmp TWI_BUS_CD ; Two-wire Bus Connect/Disconnect Handler 0x0020 jmp TWI ; Two-wire Serial Interface Handler 0x0022 jmp VADC ; Voltage ADC Conversion Complete Handler 0x0024 jmp CCADC_CONV ; CC-ADC Instantaneous Current Conversion Complete Handler 0x0026 jmp CCADC_REC_CUR ; CC-ADC Regular Current Handler 0x0028 jmp CCADC_ACC ; CC-ADC Accumulate Current Conversion Complete Handler 0x002A jmp EE_RDY ; EEPROM Ready Handler 0x002C jmp SPM_RDY ; Store Program Memory Ready Handler ; 0x002E RESET: ldi r16, high(RAMEND) ; Main program start 0x002F out SPH,r16 ; Set Stack Pointer to top of RAM 0x0030 ldi r16, low(RAMEND) 0x0031 out SPL,r16 0x0032 sei ; Enable interrupts 0x0033 <instr> xxx 0x0034 ... ... ... ; |
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