AT43USB325E-AC datasheet(29/109 Pages) ATMEL

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3355C–USB–4/05

AT43USB325

ing the corresponding interrupt handling vector. Alternatively, OCF1B is cleared by writing a

logic one to the flag. When the I-bit in SREG, and OCIE1B (Timer/Counter1 Compare match

InterruptB Enable), and the OCF1B are set (one), the Timer/Counter1 Compare B match Inter-

rupt is executed.

• Bit 4 – Res: Reserved Bit

This bit is a reserved bit in the AT43USB325 and always reads zero.

• Bit 3 – ICF1: - Input Capture Flag 1

The ICF1 bit is set (one) to flag an input capture event, indicating that the Timer/Counter1 value

has been transferred to the input capture register - ICR1. ICF1 is cleared by the hardware when

executing the corresponding interrupt handling vector. Alternatively, ICF1 is cleared by writing a

logic one to the flag. When the SREG I-bit, and TICIE1 (Timer/Counter1 Input Capture Interrupt

Enable), and ICF1 are set (one), the Timer/Counter1 Capture Interrupt is executed.

• Bit 2 – Res: Reserved Bit

This bit is a reserved bit in the AT43USB325 and always reads zero.

• Bit 1 – TOV: Timer/Counter0 Overflow Flag

The bit TOV0 is set (one) when an overflow occurs in Timer/Counter0. TOV0 is cleared by the

hardware when executing the corresponding interrupt handling vector. Alternatively, TOV0 is

cleared by writing a logic one to the flag. When the SREG I- bit, and TOIE0 (Timer/Counter0

Overflow Interrupt Enable), and TOV0 are set (one), the Timer/Counter0 Overflow interrupt is

executed.

• Bit 0 – Res: Reserved Bit

This bit is a reserved bit in the AT43USB325 and always reads zero.

4.10

External Interrupts

The external interrupts are triggered by the INT1 and INTA/B/C/D pins. Observe that, if enabled,

the INT1 interrupt will trigger even if the INT1 pin is configured as an output. This feature pro-

vides a way of generating a software interrupt. A falling or rising edge or a low level can trigger

the external interrupts. This is set up as indicated in the specification for the MCU Control Regis-

ter – MCUCR and the Interrupt Sense Control Register – ISCR. When INT1 is enabled and is

configured as level triggered, the interrupt will trigger as long as the pin is held low. INT1 is set

up as described in the specification for the MCU Control Register – MCUCR.

4.11

Interrupt Response Time

The interrupt execution response for all the enabled AVR interrupts is 4 clock cycles minimum. 4

clock cycles after the interrupt flag has been set, the program vector address for the actual inter-

rupt handling routine is executed. During this 4 clock cycle period, the Program Counter (2

bytes) is pushed onto the Stack, and the Stack Pointer is decremented by 2. The vector is nor-

mally a jump to the interrupt routine, and this jump takes 3 clock cycles. If an interrupt occurs

during execution of a multi-cycle instruction, this instruction is completed before the interrupt is

served.

A return from an interrupt handling routine (same as for a subroutine call routine) takes 4 clock

cycles. During these 4 clock cycles, the Program Counter (2 bytes) is popped back from the

Stack, the Stack Pointer is incremented by 2, and the I flag in SREG is set. When the AVR exits

AT43USB325E-AC Datasheet(PDF) 29 Page - ATMEL Corporation

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