MPXY8300 datasheet(22/164 Pages) FREESCALE

22 / 164 page

MPXY8300 Series

Sensors

Freescale Semiconductor

Figure 4-3 FLASH Burst Program Flowchart

4.6.5

Access Errors

An access error occurs whenever the command execution protocol is violated.

Any of the following specific actions will cause the access error flag (FACCERR) in FSTAT to be set. FACCERR must be cleared

by writing a 1 to FACCERR in FSTAT before any command can be processed.

•

Writing to a FLASH address before the internal FLASH clock frequency has been set by writing to the FCDIV register

•

Writing to a FLASH address while FCBEF is not set (A new command cannot be started until the command buffer is

empty.)

•

Writing a second time to a FLASH address before launching the previous command (There is only one write to FLASH

for every command.)

•

Writing a second time to FCMD before launching the previous command (There is only one write to FCMD for every

command.)

•

Writing to any FLASH control register other than FCMD after writing to a FLASH address

•

Writing any command code other than the five allowed codes (0x05, 0x20, 0x25, 0x40, or 0x41) to FCMD

•

Accessing (read or write) any FLASH control register other than the write to FSTAT (to clear FCBEF and launch the

command) after writing the command to FCMD.

•

The MCU enters stop mode while a program or erase command is in progress (The command is aborted.)

FCBEF?

START

WRITE TO FLASH

TO BUFFER ADDRESS AND DATA

WRITE COMMAND ($25) TO FCMD

YES

FPVIO OR

WRITE 1 TO FCBEF

TO LAUNCH COMMAND

AND CLEAR FCBEF (Note 2)

YES

NEW BURST COMMAND?

FCCF?

ERROR EXIT

DONE

Note 2: Wait at least four bus cycles before

FACCERR?

CLEAR ERROR

FACCERR?

Note 1: Required only once after reset.

WRITE TO FCDIV (Note 1)

checking FCBEF or FCCF.

FLASH BURST

PROGRAM FLOW

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