MPXY8300 datasheet(72/164 Pages) FREESCALE

72 / 164 page

MPXY8300 Series

Sensors

Freescale Semiconductor

If the associated port pin is not stable for at least two bus clock cycles before changing to input capture mode, it is possible to

get an unexpected indication of an edge trigger. Typically, a program would clear status flags after changing channel configuration

bits and before enabling channel interrupts or using the status flags to avoid any unexpected behavior.

Table 9-4 TPMCnSC Register Field Descriptions

Field

Description

CHnF

Channel n Flag — When channel n is configured for input capture, this flag bit is set when an active edge

occurs on the channel n pin. When channel n is an output compare or edge-aligned PWM channel, CHnF is set

when the value in the TPM counter registers matches the value in the TPM channel n value registers. This flag

is seldom used with center-aligned PWMs because it is set every time the counter matches the channel value

A corresponding interrupt is requested when CHnF is set and interrupts are enabled (CHnIE = 1). Clear CHnF

by reading TPMCnSC while CHnF is set and then writing a 0 to CHnF. If another interrupt request occurs before

the clearing sequence is complete, the sequence is reset so CHnF would remain set after the clear sequence

was completed for the earlier CHnF. This is done so a CHnF interrupt request cannot be lost by clearing a pre-

vious CHnF. Reset clears CHnF. Writing a 1 to CHnF has no effect.

No input capture or output compare event occurred on channel n

Input capture or output compare event occurred on channel n

CHnIE

Channel n Interrupt Enable — This read/write bit enables interrupts from channel n. Reset clears CHnIE.

Channel n interrupt requests disabled (use software polling)

Channel n interrupt requests enabled

MSnB

Mode Select B for TPM Channel n — When CPWMS = 0, MSnB = 1 configures TPM channel n for edge-

aligned PWM mode. For a summary of channel mode and setup controls, refer to Table 9-5.

MSnA

Mode Select A for TPM Channel n — When CPWMS = 0 and MSnB = 0, MSnA configures TPM channel n for

input capture mode or output compare mode. Refer to Table 9-5 for a summary of channel mode and setup

controls.

3:2

ELSn[B:A]

Edge/Level Select Bits — Depending on the operating mode for the timer channel as set by

CPWMS:MSnB:MSnA and shown in Table 9-5, these bits select the polarity of the input edge that triggers an

input capture event, select the level that will be driven in response to an output compare match, or select the

polarity of the PWM output.

Setting ELSnB:ELSnA to 0:0 configures the related timer pin as a general-purpose I/O pin unrelated to any

timer channel functions. This function is typically used to temporarily disable an input capture channel or to

make the timer pin available as a general-purpose I/O pin when the associated timer channel is set up as a soft-

ware timer that does not require the use of a pin.

Table 9-5 Mode, Edge, and Level Selection

CPWMS

MSnB:MSnA

ELSnB:ELSnA

Mode

Configuration

Pin not used for TPM channel; use as an external clock for the TPM or

revert to general-purpose I/O

Input capture

Capture on rising edge only

Capture on falling edge only

Capture on rising or falling edge

Output compare Software compare only

Toggle output on compare

Clear output on compare

Set output on compare

Edge-aligned

PWM

High-true pulses (clear output on compare)

Low-true pulses (set output on compare)

Center-aligned

PWM

High-true pulses (clear output on compare-up)

Low-true pulses (set output on compare-up)

MPXY8300 Datasheet(PDF) 72 Page - Freescale Semiconductor, Inc

MPXY8300 Datasheet(HTML) 72 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL